Commit Graph

35 Commits

Author SHA1 Message Date
tangxifan b87b7a99c5 [Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators 2021-09-29 20:21:46 -07:00
tangxifan 5da8f1db73 [Engine] Upgrading fabric generator to connect nets between top module and BL/WL shift register modules 2021-09-28 23:27:47 -07:00
tangxifan be4c850d2d [Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs 2021-09-24 12:03:35 -07:00
tangxifan ed80d6b3f4 [Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier 2021-09-05 13:23:38 -07:00
tangxifan cf2e479d18 [Engine] Refactor the TopModuleNumConfigBits data structure 2021-09-05 12:01:38 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan 2c5634ee76 [Tool] Change pin naming of grid modules to be related to architecture port names 2021-03-13 20:05:18 -07:00
tangxifan e6091fb3ff [Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition 2021-02-18 21:56:30 -07:00
tangxifan 5be9e9b736 [Tool] Adapted tools to support I/O in center grid 2020-12-04 18:50:13 -07:00
tangxifan 088198c861 [Tool] enhance error checking in fabric key parser 2020-11-13 10:56:00 -07:00
tangxifan 9cbc374b33 [Tool] Add check codes for tile annotation 2020-11-11 12:03:13 -07:00
tangxifan cbb1545ee3 [Tool] Add connection builder for tile global ports to top-level module 2020-11-10 16:59:00 -07:00
tangxifan 4a2874b2bc [Tool] Refactor the codes for walking through io blocks 2020-11-03 13:21:50 -07:00
tangxifan e4d974c5c8 [Tool] Split io location mapping builder from fabric builder 2020-11-02 18:27:34 -07:00
tangxifan 448e88645a [Tool] Support multiple memory banks in top-level module 2020-10-29 12:42:03 -06:00
tangxifan bd49ea95d4 [Tool] Add function to comput configuration bits by region 2020-10-28 12:37:09 -06:00
tangxifan 446f982410 [Tool] Add warning when number of regions defined in fabric key is different than architecture 2020-10-28 11:43:05 -06:00
tangxifan f93d46a870 [OpenFPGA Tool] Add multiple configuration chain support in top module builder 2020-09-28 19:03:19 -06:00
tangxifan 552dddffd0 [OpenFPGA Tool] Support configurable regions in module manager 2020-09-28 18:13:07 -06:00
tangxifan 824b56f14c fabric key can now accept instance name only; decoders are no longer part of the key 2020-07-06 16:42:33 -06:00
tangxifan 83e26adf90 add module usage types for future FPGA-SPICE development 2020-07-04 22:33:54 -06:00
tangxifan adee87569d enable fast bitstream building by creating a frame view of fabric 2020-07-02 16:25:36 -06:00
tangxifan e7d5736269 add profile time to top module builder for better spot on runtime/memory overhead sources 2020-06-29 23:17:03 -06:00
tangxifan 66746f69da optimizing memory efficiency by reserving nets in module manager 2020-06-29 21:27:43 -06:00
tangxifan a5055e9d26 add support about loading external fabric key 2020-06-12 13:03:11 -06:00
tangxifan 9dbf536306 add shuffled configurable children support for top module 2020-06-12 11:16:53 -06:00
tangxifan 5368485bd6 keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level 2020-06-11 19:31:14 -06:00
tangxifan fa8dfc1fbd add configuration protocol ports to top module for memory bank organization 2020-06-11 19:31:13 -06:00
tangxifan ed2325ec9e add frame decoder build-up to top-level module 2020-06-11 19:31:09 -06:00
tangxifan 290dd1a8a6 add frame decoder builder to all the module graph builder except the top-level 2020-06-11 19:31:09 -06:00
tangxifan e601a648cc relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics 2020-03-27 19:07:34 -06:00
tangxifan b6bdf78d95 bug fixed for heterogeneous block instances in top module 2020-03-24 17:39:26 -06:00
tangxifan a6c2d2c7d1 bug fixed for io location mapping 2020-02-28 14:46:01 -07:00
tangxifan b3796b0818 build io location map 2020-02-26 19:58:18 -07:00
tangxifan 85627dc128 put build top module online 2020-02-15 14:13:32 -07:00