AurelienUoU
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a3656dde45
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Add missing Verilog source, Archictecture folder and Testbenches correction
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2019-05-13 16:41:35 -06:00 |
tangxifan
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46d44fa42a
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Update VPR7 X2P with new engine
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2019-04-26 12:23:47 -06:00 |
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AurelienUoU
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7ff245448b
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Add new benchmark and modify go.sh to use it
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2018-12-26 04:24:26 -07:00 |
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tangxifan
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ee6b1d6cd6
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adapt arch xml and act for demo
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2018-12-13 22:46:40 -07:00 |
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tangxifan
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3d9e913e4e
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add a benchmark fifo
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2018-12-12 16:45:33 -07:00 |
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AurelienUoU
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cc5a01d476
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Fix waveform generation + add benchmark and update go.sh
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2018-12-11 22:21:39 -07:00 |
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AurelienUoU
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317c3b59c9
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Update go.sh and upload pip_add.v
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2018-12-11 15:47:05 -07:00 |
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AurelienUoU
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c2c4e78639
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Add pip_add benchmark
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2018-12-11 15:29:48 -07:00 |
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AurelienUoU
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7020d9b4b6
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Edit waveform generator + fix clock mapping in autochecked testbench
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2018-12-09 15:48:59 -07:00 |
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tangxifan
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d683134b12
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rename customized vpr7 to vpr7 XML to Production
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2018-09-17 23:10:45 -06:00 |