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4043 Commits

Author SHA1 Message Date
tangxifan 1fd399736d [Tool] Patch FPGA-SDC to consider time unit in global port timing constraints 2021-05-27 10:26:20 -06:00
tangxifan 537b73ba6e
Merge pull request #314 from lnis-uofu/doc_patch 
Documentation update on example circuit models for data memories
 2021-05-24 19:17:17 -06:00
tangxifan 16ae23f33e [Doc] Update notes about compilation guidelines 2021-05-24 16:26:59 -06:00
tangxifan 9b40e74e25 [Doc] Add example circuit models for multipliers and update technical highlight with links to the examples 2021-05-24 15:24:50 -06:00
tangxifan 21a18069a1 [Doc] Add example circuit about dual-port RAMs to documentation; Updated technical highlights by providing links to the examples 2021-05-24 14:50:55 -06:00
tangxifan b6b98a75b8 [Doc] Add example circuit model about multi-mode flip-flops; Separate data-path FF circuit model and configuration-chain FF circuit model; 2021-05-24 13:03:40 -06:00
Andrew Pond 12b44e0eca added configuration benchmark files 2021-05-13 10:04:23 -06:00
tangxifan a2b2642ec1
Merge pull request #311 from lnis-uofu/report_bitstream 
Report bitstream distribution
 2021-05-07 13:09:13 -06:00
tangxifan c33ca464dc [Test] Deploy new tests to regression test 2021-05-07 12:06:46 -06:00
tangxifan 2baf3ddd2f [Test] Add test cases for 'report_bitstream_distribution' command 2021-05-07 12:06:24 -06:00
tangxifan 7dc7c1b4f5 [Script] Add example openfpga shell script showing how to use 'report_bitstream_distribution' command 2021-05-07 12:05:47 -06:00
tangxifan 24f83f0058 [Doc] Update documentation about the new command 'report_bitstream_distribution' 2021-05-07 11:54:33 -06:00
tangxifan c4ecc9ee7c [Tool] Patch data type of report bitstream distribution command-line option 2021-05-07 11:44:01 -06:00
tangxifan db9bb9124e [Tool] Add report bitstream distribution command to openfpga shell 2021-05-07 11:41:25 -06:00
tangxifan 01b3a96e4b [Tool] Add report bitstream distribution functionality to architecture bitstream library 2021-05-07 11:22:01 -06:00
ganeshgore 9f58f926c8
Merge pull request #310 from lnis-uofu/micro_benchmarks 
Introduce Micro benchmark: 1-bit Blinking
 2021-05-06 17:24:44 -06:00
tangxifan f1658cb735 [Test] Deploy blinking to test cases 2021-05-06 15:17:45 -06:00
tangxifan 16fff90607 [Benchmark] Add microbenchmark 1-bit blinking 2021-05-06 15:17:27 -06:00
tangxifan 7ef98a94ea
Merge pull request #309 from lnis-uofu/micro_benchmarks 
Micro benchmarks for dual port BRAMs
 2021-04-28 16:23:31 -06:00
tangxifan f77b81fe5b [Arch] recover the mem16k arch as it is used in other test cases 2021-04-28 15:05:30 -06:00
tangxifan bc34efe337 [Arch] Bug fix in the architecture using BRAM spanning two columns 2021-04-28 14:32:17 -06:00
tangxifan a5e40fbb21
Merge branch 'master' into micro_benchmarks 2021-04-28 14:27:58 -06:00
tangxifan 870432e7f1 [Test] Patch regression test script due to the change of DPRAM test case 2021-04-28 12:45:52 -06:00
tangxifan b72d4bd807 [Test] Update test case for 1kbit DPRAM architectures 2021-04-28 11:28:53 -06:00
tangxifan 117cea295d [Arch] Patch architecture to be compatible with pin names of DPRAM cell 2021-04-28 11:28:23 -06:00
tangxifan a571b063b6 [Benchmark] Add 1k DPRAM benchmark which can fit new arch 2021-04-28 11:26:31 -06:00
tangxifan c24edbd674 [Script] Update yosys script due to arch changes in DPRAM sizes 2021-04-28 10:55:59 -06:00
tangxifan ec4b60f3cc [Arch] Add example arch using 1-kbit DPRAM 2021-04-28 10:47:17 -06:00
tangxifan be98775ae5 [Arch] Reduce the size of DPRAM in example architecture to accelerate testing 2021-04-28 10:45:10 -06:00
tangxifan 5c729657ef [Test] Bug fix in test case for DPRAM whose width = 2 2021-04-28 10:31:22 -06:00
tangxifan 79b27a6329 [Arch] Patch arch using DPRAM block with wide = 2 2021-04-28 10:29:09 -06:00
tangxifan 63309ba72b [HDL] Patch dpram cell 2021-04-27 23:42:31 -06:00
tangxifan 411af10933 [Script] Patch yosys script for 16kbit dual port RAM 2021-04-27 23:41:47 -06:00
tangxifan 834657f2da [Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes 2021-04-27 23:41:14 -06:00
tangxifan 0bec4b3f32 [Test] Update task configuration to use proper openfpgashell script 2021-04-27 23:34:42 -06:00
tangxifan 7d059f7407 [Benchmark] Bug fix in dual port ram 16k benchmark 2021-04-27 23:33:20 -06:00
tangxifan 3c1c33bf1e [Benchmark] Add a microbenchmark just fit 16k dual port ram 2021-04-27 22:51:43 -06:00
tangxifan 7e2368158e [Benchmark] move benchmarks to microbenchmark category 2021-04-27 22:12:30 -06:00
tangxifan 5a85ec9fa0 [Benchmark] Reduce default size of FIFO to limit the number of LUTs and BRAMs to be synthesised 2021-04-27 22:09:10 -06:00
tangxifan dd46780865 [Script] Update yosys script using BRAMs 2021-04-27 21:44:27 -06:00
tangxifan fdfbdc4613 [Test] Update task configuration files to use dedicated yosys script 2021-04-27 20:05:04 -06:00
tangxifan 2802b0895c [HDL] Add yosys technology library for reworked architecture using 16k-bit DPRAM 2021-04-27 19:55:46 -06:00
tangxifan e67095edd2 [HDL] Add 16k-bit dual port ram verilog 2021-04-27 19:55:16 -06:00
tangxifan 0f8aaae2bc [Arch] Patch architecture using 16kbit dual port RAM 2021-04-27 19:54:34 -06:00
ganeshgore 3c9c089e64
Merge pull request #307 from lnis-uofu/io_map_file 
Output I/O mapping information to XML file
 2021-04-27 17:19:07 -06:00
tangxifan 1d498bb296 [Benchmark] Add a scalable micro benchmark fifo 2021-04-27 15:26:52 -06:00
tangxifan 8728fd9561 [Tool] Typo fix to resolve clang errors 2021-04-27 15:06:07 -06:00
tangxifan 1bae59dc6a [Doc] Update documentation for the write_io_mapping command 2021-04-27 14:54:57 -06:00
tangxifan 6cb4d7d720 [Test] Add the new test to regressiont test 2021-04-27 14:41:38 -06:00
tangxifan b8ced5377f [Test] Add a test case for i/o mapping writer 2021-04-27 14:41:15 -06:00