tangxifan
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68bf7a9462
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copy missing cmake modules from vtr project
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2020-01-03 21:57:19 -05:00 |
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tangxifan
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b728773159
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add vtr assert level and copy missing cmake modules from vtr project
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2020-01-03 21:56:15 -05:00 |
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tangxifan
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670642ee42
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add executable to vpr8 directory
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2020-01-03 16:50:29 -07:00 |
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tangxifan
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0f012a32a5
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add vpr8 to cmake compilation
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2020-01-03 16:45:31 -07:00 |
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tangxifan
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cd75ad384d
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2020-01-03 16:16:10 -07:00 |
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tangxifan
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f1bafffa87
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add vpr8 libs and core engine for further integration
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2020-01-03 16:14:42 -07:00 |
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tangxifan
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0a19d3f618
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add duplicate_grid_pin to travis integration
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2019-12-30 14:06:20 -07:00 |
ganeshgore
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e5627eb2ae
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Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-12-30 13:40:47 -07:00 |
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ganeshgore
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74b650e9e1
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Added fpga_x2p_duplicate_grid_pin option
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2019-12-30 12:25:28 -07:00 |
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ganeshgore
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d1e260f54f
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Spice related option added
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2019-12-30 12:16:04 -07:00 |
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ganeshgore
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c1bef00079
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-12-30 11:46:24 -07:00 |
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tangxifan
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b374056e78
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fix bug in duplicate pin addition
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2019-12-26 16:24:05 -07:00 |
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tangxifan
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ef9ed2ccbc
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added duplicate_grid_pin test case
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2019-12-26 15:08:31 -07:00 |
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tangxifan
|
7eb7be2084
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added duplicated pin support to build top module
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2019-12-26 15:02:27 -07:00 |
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tangxifan
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a28fc3013c
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reorganize the top module builder
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2019-12-26 14:37:36 -07:00 |
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tangxifan
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2306b17d9f
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added pin duplication support to grid module builder
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2019-12-25 22:24:44 -07:00 |
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tangxifan
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72d2fc6d69
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add entry to new functions for pin duplication
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2019-12-25 20:24:41 -07:00 |
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tangxifan
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d0aed4eb66
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add new option: duplicate_grid_pin
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2019-12-25 19:46:58 -07:00 |
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tangxifan
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868c573e59
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remove unused codes and parameters
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2019-12-24 20:43:29 -07:00 |
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tangxifan
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5445047863
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renamed grid and routing track naming, which are now independent from coordinates
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2019-12-24 20:17:11 -07:00 |
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tangxifan
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0eebdaf942
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add grid port naming function for modules
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2019-12-24 15:07:03 -07:00 |
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tangxifan
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43e78585ba
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add routing track naming function for unique modules
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2019-12-24 14:55:17 -07:00 |
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tangxifan
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a36cb676c2
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minor fix in ctags to include library source files
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2019-12-18 22:24:58 +08:00 |
Laboratory for Nano Integrated Systems (LNIS)
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ffe90b1da6
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Merge pull request #34 from LNIS-Projects/dev
Dev
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2019-12-04 19:26:14 -07:00 |
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tangxifan
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a04631305c
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c091b5ea99
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Merge pull request #33 from LNIS-Projects/dev
Remove legacy codes in FPGA-Verilog
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2019-12-04 16:57:19 -07:00 |
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tangxifan
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a176c253ee
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remove legacy codes in FPGA-Verilog: routing block generation
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2019-12-04 16:15:50 -07:00 |
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tangxifan
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95ea513339
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move refactored Verilog routing block generation functions to cpp files
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2019-12-04 16:09:27 -07:00 |
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tangxifan
|
322228de43
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remove legacy codes in FPGA-Verilog
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2019-12-04 16:02:43 -07:00 |
|
tangxifan
|
0dd72999d5
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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tangxifan
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0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
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13f964ea72
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add bitstream file format introduction
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2019-12-04 13:41:31 -07:00 |
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tangxifan
|
40bddd4ed7
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add FPL'19 paper to documentation reference
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2019-12-04 12:05:30 -07:00 |
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tangxifan
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323c4fdc9a
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clean up documentation build warnings and add guidelines for port naming
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2019-12-04 11:59:10 -07:00 |
AurelienUoU
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09fd2afa9c
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Adding heterogeneous synthesis requirements
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2019-12-03 16:09:26 -07:00 |
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Laboratory for Nano Integrated Systems (LNIS)
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c14dd5e392
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Merge pull request #32 from LNIS-Projects/dev
Misc Updates on regression tests and clean-up flow run
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2019-12-03 15:41:47 -07:00 |
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AurelienUoU
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32176eb352
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Adding EPFL benchmark task for openfpga_flow
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2019-12-03 14:31:53 -07:00 |
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AurelienUoU
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4b4b38d4e8
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Update openfpga.sh to allow run-flow and simulation at the same time
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2019-12-03 14:07:10 -07:00 |
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AurelienUoU
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2f14716f13
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Adding DPRAM behavioural Verilog netlist and its TB
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2019-12-03 13:58:20 -07:00 |
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tangxifan
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099863a956
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make FPGA-X2P to be run conditionally
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2019-12-03 13:50:39 -07:00 |
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tangxifan
|
eec64bb63f
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Merge pull request #31 from LNIS-Projects/dev
Update master with latest development version
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2019-12-02 17:52:03 -07:00 |
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tangxifan
|
5b4ddfb3ce
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use adapt yosys Makefile for OpenFPGA framework
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2019-11-27 14:42:47 -07:00 |
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tangxifan
|
1c7fdac3f2
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add CMakefile for yosys
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2019-11-27 14:42:18 -07:00 |
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tangxifan
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4d62dc1c3e
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Upgrade to yosys-0.9
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2019-11-27 14:40:39 -07:00 |
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Ganesh Gore
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2b465cf153
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-22 16:03:04 -07:00 |
|
tangxifan
|
8cc72536d1
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minor bug fixing
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2019-11-22 15:54:14 -07:00 |
|
tangxifan
|
96733f9ea8
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add minor comments in task file for modelsim regression tests
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2019-11-16 22:34:03 -07:00 |
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Ganesh Gore
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e6d14c8bf5
|
Merge remote-tracking branch 'origin/ganesh_dev' into dev
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2019-11-16 19:20:51 -07:00 |
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Ganesh Gore
|
3f235a16f9
|
Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2019-11-16 19:14:34 -07:00 |