tangxifan
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82e137cbe4
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[FPGA-SPICE] Add wire module SPICE writer
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2020-09-19 19:31:16 -06:00 |
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tangxifan
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1b2762386c
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[FPGA-SPICE] Bug fix for essential gate netlist writing
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2020-09-19 16:52:30 -06:00 |
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tangxifan
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26a0a769ea
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[FPGA-SPICE] Split essential gate SPICE netlists into separated files
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2020-09-19 16:45:26 -06:00 |
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tangxifan
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e102e30d19
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[FPGA-SPICE] Add support for AND/OR logic gate
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2020-09-19 16:20:21 -06:00 |
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tangxifan
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482d90018f
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[FPGA-SPICE] Create generic PMOS/NMOS instanciation function
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2020-09-19 15:33:28 -06:00 |
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tangxifan
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3262ceb276
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[FPGA-SPICE] Bug fix for pass gate transistor sizing
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2020-09-19 15:24:40 -06:00 |
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tangxifan
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aa078f079c
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[FPGA-SPICE] Restructured SPICE netlist writers for atom circuits to avoid large cpp files
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2020-09-19 15:20:19 -06:00 |
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tangxifan
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f5dadca884
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[FPGA-SPICE] Optimize the print-out of SPICE ports
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2020-09-19 15:07:48 -06:00 |
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tangxifan
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51d423e4db
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[FPGA-SPICE] Add pass-gate SPICE netlist writer
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2020-09-19 14:59:00 -06:00 |
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tangxifan
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9e4353ddf4
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[Documentation] Patch on the travis link
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2020-09-17 17:01:23 -06:00 |
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tangxifan
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ccd9ebe71b
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[Documentation] Use travis.com in CI badge as travis.org will be deprecated by the end of 2020
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2020-09-17 16:59:20 -06:00 |
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tangxifan
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681e80d4b6
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[Regression tests] update frac_lut test case using more representative benchmarks
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2020-09-17 10:39:22 -06:00 |
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tangxifan
|
367cf59efd
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[Benchmark] Bug fix in the and2_or2 benchmark
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2020-09-17 10:35:13 -06:00 |
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tangxifan
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de48b8c7b2
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[Benchmark] Add a new micro benchmark to test fracturable LUTs
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2020-09-17 10:21:25 -06:00 |
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tangxifan
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9cfb2f52ef
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[OpenFPGA code] bug fix for fully equivalent outputs of pb_type
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2020-09-16 19:26:46 -06:00 |
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tangxifan
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ca1bafc688
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[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
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2020-09-16 19:26:12 -06:00 |
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tangxifan
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2aff461f59
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[Regression Tests] Deploy no local routing test case to CI
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2020-09-16 18:09:24 -06:00 |
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tangxifan
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c22d8e2421
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[Architecture] Bug fix in no local routing architecture
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2020-09-16 18:07:52 -06:00 |
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tangxifan
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c40c9f5876
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[Regression test] add test case for no local routing architecture
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2020-09-16 18:05:33 -06:00 |
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tangxifan
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f5b7ac6269
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[OpenFPGA Architecture] Add a new architecture with no local routing
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2020-09-16 18:04:55 -06:00 |
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tangxifan
|
5fe039dd7c
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[Regression Tests] Deploy the fully connected crossbar test to CI
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2020-09-16 17:35:49 -06:00 |
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tangxifan
|
35d47ee0e7
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[Regression tests] bug fix in the test case for fully connected output crossbar
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2020-09-16 17:33:54 -06:00 |
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tangxifan
|
030d7f02f8
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[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
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2020-09-16 17:30:08 -06:00 |
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tangxifan
|
30fb99095f
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[Regression Tests] Add new test case for fully connected output crossbar
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2020-09-16 17:29:15 -06:00 |
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tangxifan
|
3c0faf0021
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[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
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2020-09-16 17:27:24 -06:00 |
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tangxifan
|
8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
|
b43cd2741d
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[Regression Tests] Add gcc-5 compatibility test to Travis CI
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2020-09-14 20:14:16 -06:00 |
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tangxifan
|
c23742c751
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 20:13:27 -06:00 |
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tangxifan
|
fc6bfdc7a2
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[OpenFPGA Code] Patch syntax compatibility for older gcc
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2020-09-14 18:55:21 -06:00 |
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tangxifan
|
d4bac95cd4
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[Regression Tests] Enable matrix eval parameter in setting up compilers
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2020-09-14 17:07:14 -06:00 |
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tangxifan
|
c08d4f5cd9
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[Regression Test] Patch travis script
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2020-09-14 16:59:08 -06:00 |
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tangxifan
|
e3559f0df9
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[Regression Test] Add compiler coverage test to CI
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2020-09-14 16:53:16 -06:00 |
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tangxifan
|
c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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2020-09-14 16:16:03 -06:00 |
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tangxifan
|
f149c88548
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[Regression Test] Deploy input buffer only multiplexer testcase to CI
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2020-09-14 16:11:48 -06:00 |
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tangxifan
|
f42411c29e
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[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
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2020-09-14 16:03:43 -06:00 |
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tangxifan
|
aaf63050bb
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
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2020-09-14 15:58:34 -06:00 |
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tangxifan
|
aa9521b23b
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[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
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2020-09-14 15:57:44 -06:00 |
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tangxifan
|
a03f2fe974
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[Regression Test] Deploy the debuf mux test case to CI
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2020-09-14 15:48:08 -06:00 |
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tangxifan
|
eecfd186f0
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[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
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2020-09-14 15:46:10 -06:00 |
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tangxifan
|
9bf0e772a3
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[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
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2020-09-14 15:45:35 -06:00 |
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tangxifan
|
7a2502ddf9
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[documentation] add more guidelines about the vpr-openfpga architecture annotation
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2020-09-02 22:47:14 -06:00 |
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tangxifan
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04070fd4ca
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[Debug aid] add pb_type full hierarchy path in the error message of architecture binding checker
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2020-09-02 22:16:10 -06:00 |
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tangxifan
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b5251ce5af
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[documentation] update motivation figure and layout licenses
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2020-09-01 11:07:50 -06:00 |
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tangxifan
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4b3142c4ee
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[Architecture File] Patch openfpga architecture with default circuit model definition
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2020-08-23 15:13:28 -06:00 |
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tangxifan
|
9101ba1021
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[Architecture Language] Update openfpga architecture files for default models
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2020-08-23 14:55:44 -06:00 |
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tangxifan
|
ac8e937a50
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[Documentation] Update for default circuit model rules
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2020-08-23 14:08:38 -06:00 |
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tangxifan
|
9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
|
b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
|
fb5a5a2448
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[documentation] remove the limitation on through channels
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2020-08-19 20:12:49 -06:00 |
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tangxifan
|
6c925dcded
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[regression test] Add more tests for thru channels and deploy to CI
|
2020-08-19 20:11:37 -06:00 |