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OpenFPGA
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5,021 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

144 Commits

Author SHA1 Message Date
coolbreeze413 9fd8c02e13 header inclusions required for MinGW windows build 2022-06-29 07:03:38 +05:30
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 3d062872de [Lib] Upgrade openfpga arch parser to error out for unsupported configuration protocol settings 2021-10-05 14:08:01 -07:00
tangxifan 977d81679d [Engine] Upgrade check codes for WL CCFF 2021-10-01 17:23:10 -07:00
tangxifan 7b010ba0f4 [Engine] Support programming shift register clock in XML syntax 2021-10-01 11:00:38 -07:00
tangxifan 4926c323e7 [Engine] Bug fix due to the optional syntax ``num_bank`` were required in XML 2021-09-29 16:32:29 -07:00
tangxifan afd03d7eb7 [Engine] Add more check codes for the CCFF circuit model used by BL/WL shift registers 2021-09-28 15:56:07 -07:00
tangxifan 0a2979d616 [Engine] Update readarchopenfpga library by adding new syntax ``num_banks`` as well as update arch writer for BL/WL protocols 2021-09-28 14:20:35 -07:00
tangxifan 5f7617b682 [Engine] Clear up compiler warnings in circuit library 2021-09-24 15:18:50 -07:00
tangxifan be4c850d2d [Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs 2021-09-24 12:03:35 -07:00
tangxifan 6645b70ae3 [Engine] Upgrade parser to support BL/WL protocols 2021-09-23 14:25:25 -07:00
tangxifan d4e3445153 [Engine] update internal data structure for new syntax in configuration protocol 2021-09-22 17:32:45 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan 148da80869 [Tool] Add new syntax about physical_pb_port_rotate_offset to support fracturable heterogeneous block mapping between operating modes and physical modes 2021-04-24 14:53:29 -06:00
tangxifan 5364b94cf8 [Tool] Update bitstream setting parser/writer to support interconnect-related syntax 2021-04-19 13:42:12 -06:00
tangxifan d877a02534 [Tool] Patch the extended bitstream setting support on mode-select bits 2021-03-10 21:28:09 -07:00
tangxifan 85640a7403 [Tool] Extend bitstream setting to support mode bits overload from eblif file 2021-03-10 20:45:48 -07:00
tangxifan 7a5dd1bc02 [Tools] Patch circuit library for dummy circuit models without any ports 2021-02-24 10:36:48 -07:00
tangxifan b2984b46ee [Tool] Upgrade libopenfpga to support superLUT-related XML syntax 2021-02-09 21:15:57 -07:00
tangxifan faabdab815 [Tool] Remove redundant tab in bitstream setting writer 2021-02-01 18:04:21 -07:00
tangxifan d5b1cc5ec7 [Tool] Bug fix in parser for bitstream settings 2021-02-01 18:01:42 -07:00
tangxifan f102e84497 [Tool] Add bitstream setting file to openfpga library 2021-02-01 17:43:46 -07:00
tangxifan b8e4675a3a [Tool] Add missing file 2021-01-15 14:48:19 -07:00
tangxifan 87b2c1f3b8 [Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation 2021-01-15 12:01:53 -07:00
tangxifan 852f5bb72e [Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers 2021-01-14 15:38:24 -07:00
tangxifan 4124777948 [Tool] Set (x,y) to be optional XML syntax in tile annotation 2021-01-09 18:56:41 -07:00
tangxifan 9a441fa5cc [Tool] Upgrade openfpga to support extended global tile port definition 2021-01-09 18:47:12 -07:00
tangxifan cc91a0aebd [Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder 2021-01-04 17:14:26 -07:00
tangxifan cb34be0dc0 [Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements 2021-01-04 15:13:54 -07:00
tangxifan d195b9e32c [Tool] Bug fix in XML syntax to define default values for a global tile port 2020-12-02 17:03:48 -07:00
tangxifan e959821813 [Tool] Enhance internal check functions for tile annotation 2020-11-11 13:59:24 -07:00
tangxifan 4dc0fb81c5 [Tool] Bug fix for clang compilation error 2020-11-10 20:32:58 -07:00
tangxifan c61ec5a8b8 [Tool] Bug fix for defining global ports from tiles 2020-11-10 20:31:14 -07:00
tangxifan 67af145455 [Tool] Add XML writer for tile annotation 2020-11-10 14:51:46 -07:00
tangxifan 6fbdbe68ae [Tool] Add tile annotation parser 2020-11-10 14:32:24 -07:00
tangxifan 0a273ffab6 [Tool] Bug fix in the tight requirements on CCFF circuit model 2020-11-06 11:16:46 -07:00
tangxifan ba0120bd76 [Tool] Remove the limitation on requiring Qb ports for CCFF 2020-11-06 11:10:04 -07:00
tangxifan 37c10f0cb5 [Tool] Add mappable I/O support and enhance I/O support 2020-11-04 20:21:49 -07:00
tangxifan f1ce816d6c [Tool] Force inout port to be mandatory for I/O cells 2020-11-02 15:14:02 -07:00
tangxifan e850dd5314 [Tool] Relax checking codes for embedded I/O circuit models 2020-11-02 13:54:31 -07:00
tangxifan 1e70825383 [OpenFPGA Tool] Add XML syntax for configurable regions 2020-09-28 13:51:43 -06:00
tangxifan 94047037c5 [OpenFPGA Tool] Streamline codes in openfpga arch parser 2020-09-27 14:33:14 -06:00
tangxifan 51d96244c6 [OpenFPGA Tool] Remove deprecated XML syntax 2020-09-26 14:30:57 -06:00
tangxifan 8b8ce22fd1 [OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library 2020-09-23 20:37:28 -06:00
tangxifan 064678fe32 [OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol 2020-09-23 20:27:52 -06:00
tangxifan f284f6f8d0 [OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs 2020-09-20 12:03:10 -06:00
tangxifan 8b6c8f73e9 [OpenFPGA code] fix bug for clang compatibility 2020-09-14 21:26:53 -06:00
tangxifan c31d36deb6 [Regression Tests] Deploy output buffer only routing multiplexer testcase to CI 2020-09-14 16:16:03 -06:00
tangxifan 9c66a35bf6 [arch language] Now circuit library will automatically identify the default circuit model if needed 2020-08-23 14:06:03 -06:00