Commit Graph

17 Commits

Author SHA1 Message Date
tangxifan dcc96bf7f5 bug fixing 2019-07-17 08:25:52 -06:00
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
Baudouin Chauviere 69014704ef Explicit verilog final push 2019-07-16 13:13:30 -06:00
Baudouin Chauviere 25f5bc7792 Latest version, not stable yet but close 2019-07-09 08:34:01 -06:00
Baudouin Chauviere 8f5ad2eb67 Snapshot of progress 2019-07-02 10:10:48 -06:00
Baudouin Chauviere f189ef1d8f Done with the submodules 2019-07-01 14:24:09 -06:00
Baudouin Chauviere 370ce23646 Mux explicit verilog done 2019-07-01 13:58:24 -06:00
Baudouin Chauviere 863e8677c0 Further add new functions to tree 2019-07-01 12:12:36 -06:00
AurelienUoU ec504049ef Update Testbenches to increase accuracy + commented compact routing option until debug 2019-06-26 10:01:12 -06:00
tangxifan 1776ae3ec8 add explicit port mapping for inverters of memory decoders 2019-06-10 17:36:14 -06:00
tangxifan f43955037c remove input port requirements for SRAM circuit module 2019-06-10 15:29:44 -06:00
giacomin ceee28226e Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-20 16:47:07 -06:00
giacomin 8b520349e7 fixed a bug for rram based fpga when using explicit verilog port mapping 2019-05-20 16:44:47 -06:00
AurelienUoU 99beeb48cc Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb 2019-05-13 16:42:27 -06:00
AurelienUoU a3656dde45 Add missing Verilog source, Archictecture folder and Testbenches correction 2019-05-13 16:41:35 -06:00
Baudouin Chauviere 2019840d7c cleaned unused variables 2019-05-13 14:45:02 -06:00
tangxifan 46d44fa42a Update VPR7 X2P with new engine 2019-04-26 12:23:47 -06:00