tangxifan
|
05d276097e
|
critical bug fixed in openfpga shell so that our command parse results should be reset each time before parsing a line
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b8a79c563d
|
bug fix in the SDC port generation
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
84d24ad075
|
bug fix in pnr sdc grid writer for module paths in hierarchical view
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
99fa51cb49
|
bug fixed in the SDC CB hierarchy writer
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
10e1a4b2fe
|
format fix in the fabric hierarchy and grid SDC hierarchy to be complaint to YAML format
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
cc6d988872
|
bug fix in grid SDC generator
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b167c85980
|
fully expand grid hierarchy in SDC writer
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
55518f4cec
|
minor fix in the sdc hierarchy writer for grids
|
2020-06-11 19:31:05 -06:00 |
|
tangxifan
|
b57a90a6ca
|
add SDC hierarchy writer for grids and now support flatten hierarchy in grid timing constraints
|
2020-06-11 19:31:05 -06:00 |
|
Xifan Tang
|
24934aff86
|
update documentation on the depth option for fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
5a8c05378e
|
add --depth option to fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
d9dc7160a7
|
minor fix on the hierarchy writer in SDC generator
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
752470c2da
|
update documentation on write hierarchy command and options
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
17c254a370
|
add missing file to follow up the previous commit
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
c651df6421
|
add hierarchy writer to SDC generator
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
1943929353
|
add write_fabric_hierarchy to regression tests
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
6aff33dd35
|
add fabric hierarchy writer
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
0985c720e9
|
remove regexp in SDC generation.
|
2020-06-11 19:31:04 -06:00 |
|
tangxifan
|
98fbcb5410
|
add time unit test for SDC generation to CI
|
2020-06-11 19:31:04 -06:00 |
|
Xifan Tang
|
ac378febef
|
update doc about time units in SDC generator
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
8726c618eb
|
add time unit support on SDC generator. Now users can define time_unit thru cmd-line options
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
47f040822f
|
deploy the tests to CI
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
4083fae41a
|
add new test cases about user-defined simulation settings
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
2fbf9c2cfc
|
change to a higher simulation clock speed to accelerate CI verification.
Later, we should place simulation information in another XML so that we can reuse that easily
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
0e44cf3ea3
|
now SDC to disable routing multiplexer outputs can use wildcards
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
609115e51f
|
now hierarchical SDC generation is applicable to CB timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
Xifan Tang
|
d18e924a89
|
Update documentation on new fpga_sdc option
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7e82c23f52
|
now add SDC generator supports both hierarchical and flatten in writing timing constraints
|
2020-06-11 19:31:03 -06:00 |
|
tangxifan
|
7503c58fb2
|
small fix on SDC generator for SB which do not exist in FPGA
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
d0793d9029
|
now disable_sb_output support wildcard
|
2020-06-11 19:31:02 -06:00 |
|
Xifan Tang
|
ecdbdcb592
|
update documentation on new SDC options
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
8695c5ee78
|
add options to use general-purpose wildcards in SDC generator
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
facd87dafe
|
use wildcard in SDC generation for multiple-instanced-blocks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
1e2226e1c3
|
now use explicit port mapping in the verilog testbenches for reference benchmarks
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889bc8dbe8
|
add more test cases about LUT design and deploy to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
1d35ac8086
|
deploy local encoder to CI
|
2020-06-11 19:31:02 -06:00 |
|
tangxifan
|
889f179ce7
|
add local encoder test case
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
98a658a013
|
bug fixed in routing_test.v. Deployed to regression tests
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
f6cea1e17c
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
|
CHARAS SAMY
|
3c781b18d3
|
Added routing benchmark
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
69306faf22
|
add a new include netlist for all the fabric-related netlists
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
5c851a8467
|
deploy the fabric/testbench generation only cases to travis
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
a3fe6a9fcb
|
update travis script with example run on MCNC big20
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
|
2020-06-11 19:30:55 -06:00 |
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
49edeb119c
|
BugFix : Relative path for refrence benchmark fixed
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
890ead91b9
|
Fixed modelsim include references
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
8f5a684b10
|
removed redundant include files in all the verilog netlists except the top one
|
2020-06-11 19:28:13 -06:00 |