tangxifan
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d877a02534
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[Tool] Patch the extended bitstream setting support on mode-select bits
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2021-03-10 21:28:09 -07:00 |
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tangxifan
|
85640a7403
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[Tool] Extend bitstream setting to support mode bits overload from eblif file
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2021-03-10 20:45:48 -07:00 |
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tangxifan
|
7a5dd1bc02
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[Tools] Patch circuit library for dummy circuit models without any ports
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2021-02-24 10:36:48 -07:00 |
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tangxifan
|
b2984b46ee
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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
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2021-02-09 21:15:57 -07:00 |
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tangxifan
|
faabdab815
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[Tool] Remove redundant tab in bitstream setting writer
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2021-02-01 18:04:21 -07:00 |
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tangxifan
|
d5b1cc5ec7
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[Tool] Bug fix in parser for bitstream settings
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2021-02-01 18:01:42 -07:00 |
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tangxifan
|
f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
|
b8e4675a3a
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[Tool] Add missing file
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2021-01-15 14:48:19 -07:00 |
|
tangxifan
|
87b2c1f3b8
|
[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
|
852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
|
4124777948
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[Tool] Set (x,y) to be optional XML syntax in tile annotation
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2021-01-09 18:56:41 -07:00 |
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tangxifan
|
9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
|
cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
|
cb34be0dc0
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[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
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2021-01-04 15:13:54 -07:00 |
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tangxifan
|
d195b9e32c
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[Tool] Bug fix in XML syntax to define default values for a global tile port
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2020-12-02 17:03:48 -07:00 |
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tangxifan
|
e959821813
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[Tool] Enhance internal check functions for tile annotation
|
2020-11-11 13:59:24 -07:00 |
|
tangxifan
|
4dc0fb81c5
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[Tool] Bug fix for clang compilation error
|
2020-11-10 20:32:58 -07:00 |
|
tangxifan
|
c61ec5a8b8
|
[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
|
tangxifan
|
67af145455
|
[Tool] Add XML writer for tile annotation
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2020-11-10 14:51:46 -07:00 |
|
tangxifan
|
6fbdbe68ae
|
[Tool] Add tile annotation parser
|
2020-11-10 14:32:24 -07:00 |
|
tangxifan
|
0a273ffab6
|
[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-06 11:16:46 -07:00 |
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tangxifan
|
ba0120bd76
|
[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
|
37c10f0cb5
|
[Tool] Add mappable I/O support and enhance I/O support
|
2020-11-04 20:21:49 -07:00 |
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tangxifan
|
f1ce816d6c
|
[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
|
e850dd5314
|
[Tool] Relax checking codes for embedded I/O circuit models
|
2020-11-02 13:54:31 -07:00 |
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tangxifan
|
1e70825383
|
[OpenFPGA Tool] Add XML syntax for configurable regions
|
2020-09-28 13:51:43 -06:00 |
|
tangxifan
|
94047037c5
|
[OpenFPGA Tool] Streamline codes in openfpga arch parser
|
2020-09-27 14:33:14 -06:00 |
|
tangxifan
|
51d96244c6
|
[OpenFPGA Tool] Remove deprecated XML syntax
|
2020-09-26 14:30:57 -06:00 |
|
tangxifan
|
8b8ce22fd1
|
[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
|
2020-09-23 20:37:28 -06:00 |
|
tangxifan
|
064678fe32
|
[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
|
2020-09-23 20:27:52 -06:00 |
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tangxifan
|
f284f6f8d0
|
[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
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tangxifan
|
8b6c8f73e9
|
[OpenFPGA code] fix bug for clang compatibility
|
2020-09-14 21:26:53 -06:00 |
|
tangxifan
|
c31d36deb6
|
[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
|
2020-09-14 16:16:03 -06:00 |
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tangxifan
|
9c66a35bf6
|
[arch language] Now circuit library will automatically identify the default circuit model if needed
|
2020-08-23 14:06:03 -06:00 |
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tangxifan
|
b83319bf14
|
[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
|
2020-08-23 13:48:22 -06:00 |
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tangxifan
|
161d660837
|
update documentation for the initial offset when mapping physical pins
|
2020-08-19 15:00:46 -06:00 |
|
tangxifan
|
3eea12ceae
|
added a new XML syntax: initial offset for physical mode pin mapping
|
2020-08-19 14:43:44 -06:00 |
|
tangxifan
|
2712c354a9
|
now physical pb_port binding support multiple ports
|
2020-08-18 12:38:56 -06:00 |
|
tangxifan
|
a3d22c56e3
|
bug fix in FPGA-SPICE
|
2020-07-24 19:51:32 -06:00 |
|
tangxifan
|
6d046efc52
|
add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
|
2020-07-24 16:25:27 -06:00 |
|
tangxifan
|
f573fa3ee0
|
move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
|
2020-07-22 18:47:12 -06:00 |
|
tangxifan
|
de4586217f
|
now device binding is not mandatory for circuit models
|
2020-07-14 12:04:22 -06:00 |
|
tangxifan
|
e2b492f184
|
add circuit model tech binding
|
2020-07-13 20:35:10 -06:00 |
|
tangxifan
|
f081cef495
|
add fabric key library
|
2020-06-12 00:07:04 -06:00 |
|
tangxifan
|
58807bfcb3
|
remove simulation settings from openfpga arch data structure
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
f26550141f
|
add missing files
|
2020-06-11 19:31:16 -06:00 |
|
tangxifan
|
15f087598c
|
split simulation settings to a separated XML file
|
2020-06-11 19:31:15 -06:00 |
|
tangxifan
|
8267dad8ef
|
add decoder support for Z signals
|
2020-06-11 19:31:14 -06:00 |
|
tangxifan
|
65df309419
|
bug fixing for frame-based configuration protocol and rename some naming function to be generic
|
2020-06-11 19:31:10 -06:00 |
|
tangxifan
|
3a0d3b4e95
|
fix the broken CI/regression tests due to incorrect file path
|
2020-06-11 19:31:10 -06:00 |