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2,869 Commits 70 Branches 8 Tags 105 MiB
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2869 Commits

Author SHA1 Message Date
tangxifan e09e5fa6c6 [Architecture] Update fabric key for region syntax 2020-09-27 20:40:37 -06:00
tangxifan 48b2bff0d9 [OpenFPGA Tool] Update fabric key data structure to support regions 2020-09-27 20:08:11 -06:00
tangxifan bbdea4a46b [Regression Test] Remove out-of-update sub modules 2020-09-27 19:23:13 -06:00
Laboratory for Nano Integrated Systems (LNIS) 2ea7b7ea96
Merge pull request #97 from LNIS-Projects/dev 
Deprecated Code Removal
 2020-09-27 17:55:26 -06:00
tangxifan e95eacfbd9 Merge branch 'dev' into ganesh_dev 2020-09-27 17:01:57 -06:00
tangxifan 94047037c5 [OpenFPGA Tool] Streamline codes in openfpga arch parser 2020-09-27 14:33:14 -06:00
tangxifan 94a1324f05 [Documentation] Remove deprecated XML syntax 2020-09-26 14:31:57 -06:00
tangxifan 51d96244c6 [OpenFPGA Tool] Remove deprecated XML syntax 2020-09-26 14:30:57 -06:00
Laboratory for Nano Integrated Systems (LNIS) 73a4e1fafb
Merge pull request #96 from LNIS-Projects/dev 
[OpenFPGA Tool] Add self-testing Verilog codes for configuration done…
 2020-09-26 13:16:47 -06:00
tangxifan 154f23b108 [OpenFPGA Tool] Add self-testing Verilog codes for configuration done signals in full testbenches 2020-09-26 11:54:06 -06:00
Laboratory for Nano Integrated Systems (LNIS) c8d4be65e5
Merge pull request #94 from LNIS-Projects/dev 
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
 2020-09-25 22:28:24 -06:00
tangxifan ffd926d686 [Architecture] Update external bitstream 2020-09-25 21:30:59 -06:00
tangxifan dcbd6a0614 [Architecture] Add lib name to TGATE to test compatibility 2020-09-25 21:08:12 -06:00
tangxifan 1b4e449179 [OpenFPGA Tool] Critical bug fix for Verilog testbenches for memory bank and frame-based configuration protocol 2020-09-25 21:05:20 -06:00
tangxifan 6bea712db0 [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name 2020-09-25 14:54:51 -06:00
Laboratory for Nano Integrated Systems (LNIS) ad66f6c2f3
Merge pull request #93 from LNIS-Projects/dev 
[Architecture] Reorganize the cell netlists and update architecture f…
 2020-09-25 12:48:19 -06:00
tangxifan 019208ec0f [Architecture] Reorganize the cell netlists and update architecture files accordingly 2020-09-25 11:55:28 -06:00
Laboratory for Nano Integrated Systems (LNIS) 6262605556
Merge pull request #92 from LNIS-Projects/dev 
Smart Configuration Support and Verilog Netlist Refactoring
 2020-09-24 22:04:55 -06:00
tangxifan 20d6b2bf84 [Architecture] Remove out-of-date Verilog testbench 2020-09-24 21:14:13 -06:00
tangxifan 00bf775971 [Architecture] Bug fix for adder renaming 2020-09-24 20:54:18 -06:00
tangxifan 0a53a719bd [Architecture] Bug fix due to adder renaming 2020-09-24 20:42:24 -06:00
tangxifan e4bfa2ef51 [Architecture] Update external bitstream file 2020-09-24 20:16:50 -06:00
tangxifan bd0f0144a0 [Architecture] Rename AIB architecture for the new cell naming 2020-09-24 20:14:16 -06:00
tangxifan 8edfc79f53 [Architecture] Rename AIB cell 2020-09-24 20:11:21 -06:00
tangxifan 4ada793c84 [Architecture] Adapt openfpga architecture to follow the renamed adder cell 2020-09-24 20:09:29 -06:00
tangxifan 53187044e6 [Architecture] Rename adder cell 2020-09-24 20:07:57 -06:00
tangxifan 4a0a448171 [Architecture] Rename openfpga architecture for the I/O cell 2020-09-24 19:56:01 -06:00
tangxifan e0f9547f5b [Architecture] Rework the i/o cell Verilog HDL 2020-09-24 19:53:54 -06:00
tangxifan eb5fd1f44e [Architecture] Bug fix for architectures using scan-chain DFF cell 2020-09-24 18:37:25 -06:00
tangxifan 60a14ccbd2 [Architecture] Bug fix in architectures that use BRAM 2020-09-24 18:20:55 -06:00
tangxifan d51efd397f [Architecture] Bug fix for architectures using DFF cells 2020-09-24 18:02:42 -06:00
tangxifan 3ade6d6ff5 [Architecture] Bug fix for dff that are used in data path 2020-09-24 17:53:30 -06:00
tangxifan 3e7c88eac8 [Architecture] Bug fix in Verilog netlist for scan-chain DFF 2020-09-24 17:41:03 -06:00
tangxifan 7494556316 [Architecture] Bug fix for scan-chain FF cell 2020-09-24 17:38:16 -06:00
tangxifan 54b3f244d3 [Architecture] Remove obsolete Verilog netlists 2020-09-24 17:35:02 -06:00
tangxifan 49d6863641 [Architecture] Bug fix for scan-chain FF cell renaming 2020-09-24 17:33:14 -06:00
tangxifan 0a5369f919 [Architecture] Adapt all the architecture files to use standard DFF cell 2020-09-24 17:26:48 -06:00
tangxifan a30255b2a4 [Regression Test] Deploy new test cases to CI 2020-09-24 17:04:43 -06:00
tangxifan 19dd3778d9 [Architecture] Add test case for memory bank to use both reset and set 2020-09-24 17:04:24 -06:00
tangxifan 335f5b78c1 [Regression Test] Add test case to use both set and reset for configuration frame 2020-09-24 17:02:28 -06:00
tangxifan 2d81ff9012 [Regression test] Add configuration chain test case where both set and reset are used 2020-09-24 16:59:52 -06:00
tangxifan fc154b8560 [Architecture] Bug fix due to switching CCFF cell 2020-09-24 16:45:56 -06:00
tangxifan 4d94fcb298 [Regression Test] Bug fix in calling test cases 2020-09-24 16:38:34 -06:00
tangxifan 8468f25b23 [OpenFPGA Tool] Bug fix in the smart fast configuration strategy 2020-09-24 16:31:55 -06:00
tangxifan 79875d5a91 [Architecture] Bug fix in the configuration chain arch using both reset and set 2020-09-24 15:27:26 -06:00
tangxifan 9cb67e6097 [Architecture] Now all the configuration chain architecture use the DFFR cell by default 2020-09-24 15:19:37 -06:00
tangxifan 81965e75f6 [Architecture] Bug fix in DFF Verilog HDL 2020-09-24 14:53:21 -06:00
tangxifan 3b42fe94d6 [Architecture] Update external bitstream file 2020-09-24 14:41:44 -06:00
tangxifan 08838c4957 [Regression Test] Deploy new configuration chain test cases to CI 2020-09-24 14:36:39 -06:00
tangxifan 7fbccdd102 [Regression Tests] Add test cases for configuration chain using different DFF cells 2020-09-24 14:34:12 -06:00