tangxifan
|
9f03ecb160
|
[Test] Patch test case due to the changes in counter benchmarks
|
2021-07-02 17:57:39 -06:00 |
|
tangxifan
|
64dcdaec61
|
[Test] Update all the tasks that use counter benchmark
|
2021-07-02 17:29:13 -06:00 |
|
tangxifan
|
3cbe266c44
|
[Test] Bug fix on the test case for multi-mode FF and pin constraints
|
2021-07-02 15:27:27 -06:00 |
|
tangxifan
|
3aacce2a96
|
Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity
|
2021-07-02 14:04:42 -06:00 |
Ganesh Gore
|
edd5be2cae
|
[CI] Added testcase for benchmark variable
|
2021-07-02 12:51:34 -06:00 |
|
tangxifan
|
5286f9ba25
|
[Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking
|
2021-07-02 11:39:00 -06:00 |
ANDREW HARRIS POND
|
006b54c4bc
|
ready for merge
|
2021-07-01 15:35:39 -06:00 |
|
ANDREW HARRIS POND
|
8513b8a4ff
|
Merge branch 'verilog_testbench' of github.com:lnis-uofu/OpenFPGA into verilog_testbench
|
2021-07-01 15:29:39 -06:00 |
|
ANDREW HARRIS POND
|
2567fbee05
|
ready to merge
|
2021-07-01 15:28:59 -06:00 |
|
tangxifan
|
04ceeefb0a
|
Merge branch 'master' into verilog_testbench
|
2021-07-01 14:43:26 -06:00 |
|
ANDREW HARRIS POND
|
db9231c225
|
tests failing with initial blocks
|
2021-07-01 13:52:28 -06:00 |
|
tangxifan
|
83d177b13b
|
[Test] Deploy the newly added adder benchmarks to tests
|
2021-06-30 15:14:24 -06:00 |
|
tangxifan
|
9eeec05a1f
|
[Test] Bug fix
|
2021-06-29 19:55:07 -06:00 |
|
tangxifan
|
f32ffb6d61
|
[Test] Bug fix
|
2021-06-29 18:51:28 -06:00 |
|
tangxifan
|
c6089385b0
|
[Misc] Bug fix
|
2021-06-29 18:34:41 -06:00 |
|
tangxifan
|
5f5a03f17f
|
[Misc] Bug fix on test cases that were generating both full testbench and preconfigured testbenches
|
2021-06-29 18:28:38 -06:00 |
|
tangxifan
|
2c1692e6dc
|
[Test] Bug fix
|
2021-06-29 17:54:25 -06:00 |
|
tangxifan
|
30c2f597f2
|
[Test] Added two cases to validate testbench generation without self checking
|
2021-06-29 16:06:15 -06:00 |
|
tangxifan
|
6f0600e17f
|
[Test] Added two test cases for generating preconfigured fabric wrapper in different styles
|
2021-06-27 19:56:01 -06:00 |
|
tangxifan
|
477cba1c7e
|
Merge branch 'master' into verilog_testbench
|
2021-06-23 09:18:18 -06:00 |
|
tangxifan
|
f06017581c
|
[Test] Bug fix in counter micro benchmark tests
|
2021-06-22 16:33:50 -06:00 |
|
tangxifan
|
760570d883
|
[Test] Update counter test case for cover most counter HDL design
|
2021-06-21 18:13:18 -06:00 |
|
tangxifan
|
9c24a739be
|
[Test] Added a MAC benchmark sweeping test
|
2021-06-21 17:40:53 -06:00 |
Andrew Pond
|
3cfc42cdf9
|
added testbench CI
|
2021-06-15 14:16:31 -06:00 |
|
tangxifan
|
eed30605d7
|
[Test] patch test case
|
2021-06-09 15:20:55 -06:00 |
|
tangxifan
|
52c0ed571b
|
[Test] Patch test case to use proper template
|
2021-06-09 14:27:02 -06:00 |
|
tangxifan
|
c62666e7c3
|
[Test] Use proper template for some failing tests
|
2021-06-09 14:24:34 -06:00 |
|
tangxifan
|
462326aaa5
|
[Test] Update full testbench test case for flatten configuration protocol using 'write_full_testbench'
|
2021-06-07 21:50:00 -06:00 |
|
tangxifan
|
5ecd975ec7
|
[Test] Bug fix
|
2021-06-07 19:20:10 -06:00 |
|
tangxifan
|
9556f994b4
|
[Test] Use 'write_full_testbench' in all the memory bank -related test cases
|
2021-06-07 17:49:40 -06:00 |
|
tangxifan
|
a67196178e
|
[Test] Now use 'write_full_testbench' in configuration frame test cases
|
2021-06-07 13:58:15 -06:00 |
|
tangxifan
|
27fa15603a
|
[Tool] Patch test case due to changes in the template script
|
2021-06-04 18:17:47 -06:00 |
|
tangxifan
|
5f96d440ec
|
[Test] Deploy 'write_full_testbench' openfpga shell script to multi-headed configuration chain with auto-tuned fast configuration
|
2021-06-04 11:48:05 -06:00 |
|
tangxifan
|
ec203d3a5c
|
[Test] Deploy 'write_full_testbench' openfpga shell script to all the fast configuration chain test cases
|
2021-06-04 11:35:23 -06:00 |
|
tangxifan
|
2068291de0
|
[Test] Now deploy the 'write_full_testbench' openfpga shell script to all the configuration chain test cases
|
2021-06-04 11:32:49 -06:00 |
|
tangxifan
|
aa4e1f5f9a
|
[Test] Update test case which uses write_full_testbench openfpga shell script
|
2021-06-04 11:29:43 -06:00 |
|
tangxifan
|
ebe30fc070
|
[Test] Deploy write full testbench to multi-head configuration chain test case
|
2021-06-03 17:08:33 -06:00 |
|
tangxifan
|
1e9f6eb439
|
[Test] update configuration chain test to use new testbench
|
2021-06-03 15:53:27 -06:00 |
|
tangxifan
|
2baf3ddd2f
|
[Test] Add test cases for 'report_bitstream_distribution' command
|
2021-05-07 12:06:24 -06:00 |
|
tangxifan
|
f1658cb735
|
[Test] Deploy blinking to test cases
|
2021-05-06 15:17:45 -06:00 |
|
tangxifan
|
a5e40fbb21
|
Merge branch 'master' into micro_benchmarks
|
2021-04-28 14:27:58 -06:00 |
|
tangxifan
|
b72d4bd807
|
[Test] Update test case for 1kbit DPRAM architectures
|
2021-04-28 11:28:53 -06:00 |
|
tangxifan
|
5c729657ef
|
[Test] Bug fix in test case for DPRAM whose width = 2
|
2021-04-28 10:31:22 -06:00 |
|
tangxifan
|
0bec4b3f32
|
[Test] Update task configuration to use proper openfpgashell script
|
2021-04-27 23:34:42 -06:00 |
|
tangxifan
|
fdfbdc4613
|
[Test] Update task configuration files to use dedicated yosys script
|
2021-04-27 20:05:04 -06:00 |
|
tangxifan
|
b8ced5377f
|
[Test] Add a test case for i/o mapping writer
|
2021-04-27 14:41:15 -06:00 |
|
tangxifan
|
6291871faf
|
[Test] Added a test for the example architecture with 2x2 DSP blocks
|
2021-04-26 16:28:43 -06:00 |
|
tangxifan
|
80f98328df
|
[Test] Update test settings for architecture with fracturable DSP blocks
|
2021-04-24 15:16:50 -06:00 |
|
tangxifan
|
1c6b9a23d7
|
[Test] Add new test for multi-mode 16-bit DSP blocks
|
2021-04-24 13:29:29 -06:00 |
|
tangxifan
|
189c94ff19
|
[Test] Deploy new mac benchmarks to tests
|
2021-04-23 20:44:14 -06:00 |