tangxifan
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62b6de8437
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update the SDC of VPR7+OpenFPGA to be even with VPR8+OpenFPGA
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2020-03-25 14:44:42 -06:00 |
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tangxifan
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2f38b5cbc2
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Merge branch 'refactoring' into dev
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2020-03-08 16:23:20 -06:00 |
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tangxifan
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b219b096ee
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hotfix on removing dangling inputs from GSB, which are CLB direct output
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2020-03-08 13:54:49 -06:00 |
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tangxifan
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8b40ca2990
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Merge branch 'refactoring' into dev
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2020-03-07 17:54:13 -07:00 |
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tangxifan
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e48c2b116d
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bug fixing for duplicated grid pin names
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2020-03-07 15:46:12 -07:00 |
AurelienUoU
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aed3b01800
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Directlist extension bug fix
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2020-03-04 09:09:06 -07:00 |
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tangxifan
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fc509aa2c1
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Merge branch 'refactoring' into dev
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2020-02-27 18:03:21 -07:00 |
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tangxifan
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ae899f3b11
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bug fixed for clock names
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2020-02-27 16:51:55 -07:00 |
srtemp
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c574ab081a
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Fix GUI support with cmake 3.16
Updated cmakelist to fix gui support with cmake > 3.12. Tested on ubuntu 18.04.
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2020-01-24 10:54:37 -07:00 |
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tangxifan
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b1501223cc
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bug fixed in SDC for CBs and SBs: remove useless module names
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2020-01-17 15:33:50 -07:00 |
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tangxifan
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4bb0da5a69
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bug fixing for direct connection when pin duplication is applied
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2020-01-17 15:33:50 -07:00 |
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tangxifan
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56113e1aab
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adding XML parsing for design tech of circuit model
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2020-01-14 14:10:00 -07:00 |
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tangxifan
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2a3950470e
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remove redudant net source addition in cbs and sbs
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2020-01-08 19:43:53 -07:00 |
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tangxifan
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f1bafffa87
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add vpr8 libs and core engine for further integration
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2020-01-03 16:14:42 -07:00 |
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tangxifan
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b374056e78
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fix bug in duplicate pin addition
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2019-12-26 16:24:05 -07:00 |
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tangxifan
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7eb7be2084
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added duplicated pin support to build top module
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2019-12-26 15:02:27 -07:00 |
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tangxifan
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a28fc3013c
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reorganize the top module builder
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2019-12-26 14:37:36 -07:00 |
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tangxifan
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2306b17d9f
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added pin duplication support to grid module builder
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2019-12-25 22:24:44 -07:00 |
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tangxifan
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72d2fc6d69
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add entry to new functions for pin duplication
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2019-12-25 20:24:41 -07:00 |
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tangxifan
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d0aed4eb66
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add new option: duplicate_grid_pin
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2019-12-25 19:46:58 -07:00 |
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tangxifan
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868c573e59
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remove unused codes and parameters
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2019-12-24 20:43:29 -07:00 |
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tangxifan
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5445047863
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renamed grid and routing track naming, which are now independent from coordinates
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2019-12-24 20:17:11 -07:00 |
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tangxifan
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0eebdaf942
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add grid port naming function for modules
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2019-12-24 15:07:03 -07:00 |
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tangxifan
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43e78585ba
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add routing track naming function for unique modules
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2019-12-24 14:55:17 -07:00 |
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tangxifan
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a36cb676c2
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minor fix in ctags to include library source files
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2019-12-18 22:24:58 +08:00 |
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tangxifan
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a04631305c
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remove legacy verilog utils functions
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2019-12-04 18:02:26 -07:00 |
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tangxifan
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73386dd1a9
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refactored the Verilog header generation
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2019-12-04 17:55:05 -07:00 |
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tangxifan
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a176c253ee
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remove legacy codes in FPGA-Verilog: routing block generation
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2019-12-04 16:15:50 -07:00 |
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tangxifan
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95ea513339
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move refactored Verilog routing block generation functions to cpp files
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2019-12-04 16:09:27 -07:00 |
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tangxifan
|
322228de43
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remove legacy codes in FPGA-Verilog
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2019-12-04 16:02:43 -07:00 |
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tangxifan
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0dd72999d5
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deleting legacy codes: fpga_verilog top-level function
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2019-12-04 15:55:16 -07:00 |
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tangxifan
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0daf170e45
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refactored all the new functions to new source files, ready to delete legacy codes
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2019-12-04 15:38:42 -07:00 |
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tangxifan
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099863a956
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make FPGA-X2P to be run conditionally
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2019-12-03 13:50:39 -07:00 |
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tangxifan
|
8cc72536d1
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minor bug fixing
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2019-11-22 15:54:14 -07:00 |
|
tangxifan
|
0c2ad5ab5e
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critical bug fixed for some corner cases
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2019-11-13 20:45:41 -07:00 |
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tangxifan
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1291b99d66
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now make ini file generation more flexible: user can specify a name or use the default name
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2019-11-13 12:55:57 -07:00 |
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tangxifan
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d84cd66287
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refactored analysis SDC generator for grids
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2019-11-12 22:18:13 -07:00 |
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tangxifan
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6c58a4dd92
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refactored unused grid block SDC analysis generation
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2019-11-12 10:01:17 -07:00 |
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tangxifan
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8a57a29d2d
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refactoring analysis SDC generation for grids
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2019-11-11 22:38:11 -07:00 |
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tangxifan
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5f219b428c
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refactored analysis SDC generation for switch blocks
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2019-11-11 19:24:39 -07:00 |
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tangxifan
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876733f052
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now we use module manager to generate analysis SDC, being independent from VPR structures
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2019-11-10 21:15:34 -07:00 |
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tangxifan
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a849522be9
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refactored CB SDC analysis generation
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2019-11-10 20:15:16 -07:00 |
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tangxifan
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8e8e59b0ca
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give specific name to mux so that we can bind it to SDC generator
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2019-11-10 19:42:30 -07:00 |
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tangxifan
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3d711823e5
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refactoring SDC generator for unused CBs
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2019-11-10 18:15:13 -07:00 |
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tangxifan
|
67b3b25bea
|
refactoring analysis sdc generation
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2019-11-10 16:08:49 -07:00 |
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tangxifan
|
1f368abfbe
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refactoring analysis SDC generation
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2019-11-10 15:40:54 -07:00 |
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tangxifan
|
bcd8237263
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refactored grid PnR SDC generator
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2019-11-09 20:57:54 -07:00 |
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tangxifan
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d226d18d40
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move SDC generator for routing modules to an independent source file
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2019-11-09 11:54:05 -07:00 |
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tangxifan
|
a7f2a61d0d
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refactored CB SDC generation
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2019-11-09 11:42:38 -07:00 |
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tangxifan
|
4b5ecc516b
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refactored SDC SB constrain generation
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2019-11-09 10:52:15 -07:00 |