tangxifan
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be574b0d45
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refactored disable routing mux outputs
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2019-11-08 19:05:05 -07:00 |
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tangxifan
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e273c00c9d
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add refactored disable timing for memory cells
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2019-11-08 17:38:07 -07:00 |
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tangxifan
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ea7c981c85
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critical bugs fixed for routing module naming; and speed up local wire detection in Verilog writer
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2019-11-08 15:01:30 -07:00 |
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tangxifan
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33b3705ced
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refactoring disable outputs sdc generation
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2019-11-08 11:15:35 -07:00 |
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tangxifan
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35e718b32d
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rename backend sdc generator to be backend assistant
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2019-11-08 10:20:12 -07:00 |
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tangxifan
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14e7744fee
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start refactoring sdc generator, make it geneirc by placing it in parallel to Verilog generator
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2019-11-07 22:20:48 -07:00 |
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tangxifan
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56b4ee008e
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add test for heterogeneous FPGA and fix bugs
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2019-11-06 17:45:11 -07:00 |
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tangxifan
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4ea5756be6
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bug fixed for std cell MUX2 architecture and add the case to regression tests
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2019-11-06 16:06:47 -07:00 |
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tangxifan
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09eb373a6e
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bug fixing for autocheck top testbench where clock port is not default names
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2019-11-06 12:21:20 -07:00 |
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tangxifan
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0e620f35a4
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bug fixed for MUX2 std cells, avoid duplicated module writing
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2019-11-06 11:45:28 -07:00 |
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tangxifan
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aac4ccb279
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fixing bug for heterogeneous FPGAs
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2019-11-06 11:19:17 -07:00 |
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tangxifan
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6c04b8d959
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bug fixing for heterogeneous FPGAs
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2019-11-05 20:24:03 -07:00 |
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tangxifan
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066962fbb9
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bug fixed for clb2clb direct connection
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2019-11-05 17:41:21 -07:00 |
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tangxifan
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227fb9a1a5
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clean up the support for std cells
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2019-11-05 17:32:05 -07:00 |
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tangxifan
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aa56d95073
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bug fixed for using standard cells
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2019-11-05 17:19:57 -07:00 |
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tangxifan
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696d4a9522
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remove useless channel wire module generation
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2019-11-05 16:10:00 -07:00 |
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tangxifan
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a308a13d7c
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use prefix instead of lib_name when building modules, then use lib_name for standard cell modules
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2019-11-05 15:41:59 -07:00 |
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tangxifan
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2fbb88d25b
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remove legacy codes
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2019-11-05 13:52:42 -07:00 |
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tangxifan
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66047e4a45
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refactoring Verilog simulation flag generations
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2019-11-05 13:45:11 -07:00 |
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tangxifan
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13f2d33d37
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refactored fpga_define.v generation
Please enter the commit message for your changes. Lines starting
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2019-11-05 12:41:43 -07:00 |
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tangxifan
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8ef9e994d8
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rename source files to be what they are actually doing
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2019-11-05 12:18:23 -07:00 |
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tangxifan
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aaaf7a0d19
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remove legacy codes in writing include netlists
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2019-11-04 21:06:14 -07:00 |
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tangxifan
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ebab0e91ef
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refactored include netlist writer
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2019-11-04 20:55:30 -07:00 |
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tangxifan
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5d507ae8ee
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bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
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2019-11-04 18:05:50 -07:00 |
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tangxifan
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69bc858e62
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bring autocheck top testbench back to simulation deck, start testing
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2019-11-04 15:35:04 -07:00 |
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tangxifan
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3274a49779
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fine tuning top testbench and getting ready for testing
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2019-11-04 12:08:36 -07:00 |
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tangxifan
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d7bbae76a4
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adding stimuli to benchmark inputs in top-level testbench
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2019-11-03 20:20:14 -07:00 |
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tangxifan
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3e9968d2f0
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keep refactoring top-level testbench with auto-check features
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2019-11-03 18:59:54 -07:00 |
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tangxifan
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1fb29df1e2
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cleaning verilog file lines
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2019-11-03 17:58:18 -07:00 |
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tangxifan
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0ec465d4e1
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refactoring auto-check top Verilog testbench
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2019-11-03 17:41:29 -07:00 |
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tangxifan
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dc241e6c03
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add explicit port mapping support in testbenches; remove dangling ports in benchmarks
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2019-11-02 23:03:47 -06:00 |
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tangxifan
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05a830de1b
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bring ini writer for formality scripts back
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2019-11-02 18:56:54 -06:00 |
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tangxifan
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c681726124
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try to enlarge write buffers in ini writer, but these codes should be fully reworked
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2019-11-02 18:33:05 -06:00 |
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tangxifan
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3ad2a93539
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start bring back ini writer bit by bit
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2019-11-02 18:20:25 -06:00 |
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tangxifan
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cb74d120e7
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shadow ini writer to help debugging
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2019-11-02 17:31:05 -06:00 |
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tangxifan
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fc164abd49
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remove unused variable in sim info writer
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2019-11-02 16:35:32 -06:00 |
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tangxifan
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e1a7a2895a
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simulation ini file name can be customizable
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2019-11-02 09:59:34 -06:00 |
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tangxifan
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d5d7450ce7
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make simulation ini writing as an option
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2019-11-02 09:46:12 -06:00 |
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tangxifan
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c3db880599
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adding explicit file path to simulation info writer
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2019-11-02 09:21:02 -06:00 |
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tangxifan
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358e9892ac
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reduce some error message to warnings
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2019-11-02 00:09:13 -06:00 |
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tangxifan
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f70f387f9f
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minor tuning on ini compilation
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2019-11-01 20:51:49 -06:00 |
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tangxifan
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3669a47d3b
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reworked the ini writer
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2019-11-01 20:25:01 -06:00 |
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tangxifan
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dab66b8be7
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start adding auto check cpp files
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2019-11-01 19:49:50 -06:00 |
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tangxifan
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e2b042c61c
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
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2019-11-01 18:27:27 -06:00 |
Ganesh Gore
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a0512e40b1
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Created intermidiate file for modelsim simulation
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2019-11-01 18:20:00 -06:00 |
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tangxifan
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3ae841b80f
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start refactoring auto-check top testbench generation
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2019-11-01 16:33:12 -06:00 |
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tangxifan
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531cc064fc
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bug fixing for formal top-level testbench
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2019-11-01 10:47:40 -06:00 |
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Ganesh Gore
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da0778e813
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Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
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2019-11-01 00:46:34 -06:00 |
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tangxifan
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2dff779005
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critical bug fixed for bitstream generation for offset truth tables
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2019-10-31 20:16:08 -06:00 |
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tangxifan
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a6a3e7c36b
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adding mcnc_big20 to regression test
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2019-10-31 19:31:27 -06:00 |
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tangxifan
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858c1aefce
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try use force for Icarus
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2019-10-30 19:50:34 -06:00 |
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tangxifan
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7460dc8cab
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pass current regression tests
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2019-10-30 19:10:36 -06:00 |
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tangxifan
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55fbd72293
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many bugs have been fixed
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2019-10-30 15:50:42 -06:00 |
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tangxifan
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4398cffaaa
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single mode is working, multi-mode is under debugging
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2019-10-29 22:32:36 -06:00 |
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tangxifan
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1faacfa3cf
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keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
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2019-10-29 14:23:09 -06:00 |
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tangxifan
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7c116aac2f
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added Verilog generation for preconfig top module
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2019-10-29 13:54:35 -06:00 |
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tangxifan
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10491c4291
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bring single mode test case online with bug fixing
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2019-10-28 17:04:10 -06:00 |
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tangxifan
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fe005f1f56
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remove legacy codes for Verilog formal verification testbench generation
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2019-10-28 15:21:14 -06:00 |
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tangxifan
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c047fd3cb2
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plugged in the refactored formal verification Verilog testbench using random vectors
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2019-10-28 15:10:29 -06:00 |
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tangxifan
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ccabe4ce2a
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refactoring Verilog formal verification top testbench using random vectors
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2019-10-28 14:45:51 -06:00 |
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tangxifan
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55eea6c4d5
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rename files to be clear
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2019-10-27 20:12:48 -06:00 |
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tangxifan
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35073f48cf
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add runtime profiling to module graph builders
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2019-10-27 19:10:21 -06:00 |
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tangxifan
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2b06cfc3cf
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added fabric bitstream generator and fixed critical bugs in top module graph
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2019-10-27 18:47:33 -06:00 |
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tangxifan
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f116351831
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add instance name for each pb graph node
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2019-10-26 17:25:45 -06:00 |
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tangxifan
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7649d9228e
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fixed bugs in refactored bitstream generation
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2019-10-26 16:40:14 -06:00 |
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tangxifan
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0a9c89be0b
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add bitstream writers and start debugging
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2019-10-26 12:41:23 -06:00 |
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tangxifan
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3310bac65b
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refactored grid bitstream generation
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2019-10-25 21:49:47 -06:00 |
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tangxifan
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4b7a9dfa63
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add instance name correlation between module and bitstream generation
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2019-10-25 13:06:48 -06:00 |
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tangxifan
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0b687669c8
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affliate configuration bitstream to sb blocks
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2019-10-25 10:42:12 -06:00 |
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tangxifan
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c38513c838
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add local encoder support in bitstream generation refactoring
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2019-10-24 22:49:24 -06:00 |
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tangxifan
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97193794c4
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correct bugs in organizing child modules in top-level module
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2019-10-24 21:27:42 -06:00 |
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tangxifan
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838173f3c4
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start refactoring bitstream generator
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2019-10-24 21:01:11 -06:00 |
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tangxifan
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13c62fdcf8
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add more methods to bitstream manager (renamed from bitstream context)
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2019-10-24 15:43:29 -06:00 |
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tangxifan
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f26dbfe080
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add instance name for top-level modules to ease readability
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2019-10-23 20:24:52 -06:00 |
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tangxifan
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2787a07f0d
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start refactoring bitstream generation
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2019-10-23 17:34:21 -06:00 |
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tangxifan
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a18f1305cd
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add configurable child list to module manager
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2019-10-23 15:44:13 -06:00 |
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tangxifan
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12162a02bc
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critical bug fixing for compact routing hierarchy and top module generation
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2019-10-23 14:20:04 -06:00 |
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tangxifan
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fb2f003d5b
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add top module generation and refactored verilog generation for top module
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2019-10-23 12:16:58 -06:00 |
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tangxifan
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dafab3907e
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refactored routing module generation and verilog writing
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2019-10-23 11:46:55 -06:00 |
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tangxifan
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89c8d089a3
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add grid module generation
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2019-10-22 16:14:11 -06:00 |
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tangxifan
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9cf8683acd
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add module generation for memories
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2019-10-22 15:31:08 -06:00 |
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tangxifan
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3cf7950bc1
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add wire module generation and simplify Verilog generation for wires
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2019-10-21 20:20:34 -06:00 |
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tangxifan
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c076da9bab
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remove redundant codes
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2019-10-21 18:48:34 -06:00 |
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tangxifan
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81093f0db6
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add lut module generation and simplify Verilog generation codes
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2019-10-21 17:54:15 -06:00 |
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tangxifan
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f002f7e30f
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add const 0 and 1 module Verilog generation
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2019-10-21 14:17:09 -06:00 |
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tangxifan
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bd37f0d542
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correct bugs in decoder data port alignment to memory ports of multiplexing structure
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2019-10-21 13:16:15 -06:00 |
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tangxifan
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fe433f3e50
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bug fixed for local encoders and module nets creation
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2019-10-21 12:23:00 -06:00 |
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tangxifan
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b2f57ecf81
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plug in MUX module graph generation, still local encoders contain dangling net, bug fixing
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2019-10-21 00:00:30 -06:00 |
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tangxifan
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520e145af2
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move mux_lib to fpga_x2p_setup
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2019-10-19 19:13:52 -06:00 |
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tangxifan
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04f0fbebf7
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plug in module graph to feed verilog writers
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2019-10-18 21:59:22 -06:00 |
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tangxifan
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b1cafcdbde
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add missing files
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2019-10-18 21:04:35 -06:00 |
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tangxifan
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fbe56a06c4
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add decoder module builders
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2019-10-18 21:01:10 -06:00 |
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tangxifan
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7c1bce4b59
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add module builders for essential gates
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2019-10-18 20:41:05 -06:00 |
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tangxifan
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3b82d62d03
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start developing module graph builders
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2019-10-18 20:02:02 -06:00 |
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tangxifan
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db38f21412
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add netlist manager class
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2019-10-18 17:59:03 -06:00 |
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tangxifan
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8c1158fc5c
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refactor memory organization at the top-level module
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2019-10-18 15:33:25 -06:00 |
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tangxifan
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cfec8d70ab
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improved refactoring on clb2clb connection by considering flexible arch
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2019-10-18 11:20:09 -06:00 |
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tangxifan
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4171a674b1
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refactored clb2clb direct connects for cross-column/row
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2019-10-17 23:06:59 -06:00 |
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tangxifan
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190449c06f
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refactoring top-level module with clb2clb direct connection
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2019-10-17 17:29:04 -06:00 |
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tangxifan
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945e138e62
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debugged the gsb-grid connection in top module.
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2019-10-15 22:02:25 -06:00 |