tangxifan
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b2984b46ee
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[Tool] Upgrade libopenfpga to support superLUT-related XML syntax
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2021-02-09 21:15:57 -07:00 |
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tangxifan
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faabdab815
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[Tool] Remove redundant tab in bitstream setting writer
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2021-02-01 18:04:21 -07:00 |
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tangxifan
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d5b1cc5ec7
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[Tool] Bug fix in parser for bitstream settings
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2021-02-01 18:01:42 -07:00 |
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tangxifan
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f102e84497
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[Tool] Add bitstream setting file to openfpga library
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2021-02-01 17:43:46 -07:00 |
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tangxifan
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b8e4675a3a
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[Tool] Add missing file
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2021-01-15 14:48:19 -07:00 |
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tangxifan
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87b2c1f3b8
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[Tool] Upgrade openfpga engine to support multi-clock frequency definiton and their usage in testbench/SDC generation
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2021-01-15 12:01:53 -07:00 |
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tangxifan
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852f5bb72e
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[Tool] Update simulation setting object to support multi-clock and associated XML parsers/writers
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2021-01-14 15:38:24 -07:00 |
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tangxifan
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4124777948
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[Tool] Set (x,y) to be optional XML syntax in tile annotation
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2021-01-09 18:56:41 -07:00 |
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tangxifan
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9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
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cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
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cb34be0dc0
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[Tool] Update check functions for CCFF circuit model to be consistent with SCFF requirements
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2021-01-04 15:13:54 -07:00 |
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tangxifan
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d195b9e32c
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[Tool] Bug fix in XML syntax to define default values for a global tile port
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2020-12-02 17:03:48 -07:00 |
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tangxifan
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e959821813
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[Tool] Enhance internal check functions for tile annotation
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2020-11-11 13:59:24 -07:00 |
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tangxifan
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4dc0fb81c5
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[Tool] Bug fix for clang compilation error
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2020-11-10 20:32:58 -07:00 |
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tangxifan
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c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
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67af145455
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[Tool] Add XML writer for tile annotation
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2020-11-10 14:51:46 -07:00 |
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tangxifan
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6fbdbe68ae
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[Tool] Add tile annotation parser
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2020-11-10 14:32:24 -07:00 |
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tangxifan
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0a273ffab6
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[Tool] Bug fix in the tight requirements on CCFF circuit model
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2020-11-06 11:16:46 -07:00 |
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tangxifan
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ba0120bd76
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[Tool] Remove the limitation on requiring Qb ports for CCFF
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2020-11-06 11:10:04 -07:00 |
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tangxifan
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37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
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f1ce816d6c
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[Tool] Force inout port to be mandatory for I/O cells
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2020-11-02 15:14:02 -07:00 |
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tangxifan
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e850dd5314
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[Tool] Relax checking codes for embedded I/O circuit models
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2020-11-02 13:54:31 -07:00 |
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tangxifan
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1e70825383
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[OpenFPGA Tool] Add XML syntax for configurable regions
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2020-09-28 13:51:43 -06:00 |
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tangxifan
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94047037c5
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[OpenFPGA Tool] Streamline codes in openfpga arch parser
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2020-09-27 14:33:14 -06:00 |
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tangxifan
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51d96244c6
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[OpenFPGA Tool] Remove deprecated XML syntax
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2020-09-26 14:30:57 -06:00 |
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tangxifan
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8b8ce22fd1
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[OpenFPGA Tool] Bug fix for the edge trigger attribute in cirucit library
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2020-09-23 20:37:28 -06:00 |
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tangxifan
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064678fe32
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[OpenFPGA Tool] Add edge triggered attribute to circuit library definition. Better support for using CCFF in frame-based protocol
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2020-09-23 20:27:52 -06:00 |
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tangxifan
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f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
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2020-09-20 12:03:10 -06:00 |
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tangxifan
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8b6c8f73e9
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[OpenFPGA code] fix bug for clang compatibility
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2020-09-14 21:26:53 -06:00 |
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tangxifan
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c31d36deb6
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[Regression Tests] Deploy output buffer only routing multiplexer testcase to CI
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2020-09-14 16:16:03 -06:00 |
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tangxifan
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9c66a35bf6
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[arch language] Now circuit library will automatically identify the default circuit model if needed
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2020-08-23 14:06:03 -06:00 |
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tangxifan
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b83319bf14
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[Check codes] add check codes for default circuit models. Error out when there is no default model in a defined group
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2020-08-23 13:48:22 -06:00 |
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tangxifan
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161d660837
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update documentation for the initial offset when mapping physical pins
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2020-08-19 15:00:46 -06:00 |
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tangxifan
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3eea12ceae
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added a new XML syntax: initial offset for physical mode pin mapping
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2020-08-19 14:43:44 -06:00 |
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tangxifan
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2712c354a9
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now physical pb_port binding support multiple ports
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2020-08-18 12:38:56 -06:00 |
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tangxifan
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a3d22c56e3
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bug fix in FPGA-SPICE
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2020-07-24 19:51:32 -06:00 |
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tangxifan
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6d046efc52
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add max_width to technology library XML syntax to support multi-bin transistor in FPGA-SPICE
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2020-07-24 16:25:27 -06:00 |
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tangxifan
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f573fa3ee0
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move check codes on power gate ports to libarchopenfpga
Try to report errors to users as early as possible
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2020-07-22 18:47:12 -06:00 |
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tangxifan
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de4586217f
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now device binding is not mandatory for circuit models
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2020-07-14 12:04:22 -06:00 |
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tangxifan
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e2b492f184
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add circuit model tech binding
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2020-07-13 20:35:10 -06:00 |
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tangxifan
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f081cef495
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add fabric key library
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2020-06-12 00:07:04 -06:00 |
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tangxifan
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58807bfcb3
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remove simulation settings from openfpga arch data structure
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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f26550141f
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add missing files
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2020-06-11 19:31:16 -06:00 |
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tangxifan
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15f087598c
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split simulation settings to a separated XML file
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2020-06-11 19:31:15 -06:00 |
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tangxifan
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8267dad8ef
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add decoder support for Z signals
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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65df309419
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bug fixing for frame-based configuration protocol and rename some naming function to be generic
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a0d3b4e95
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fix the broken CI/regression tests due to incorrect file path
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2020-06-11 19:31:10 -06:00 |
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tangxifan
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3a26bb5eef
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add advanced check in configurable memories
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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62c506182c
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start developing frame-based configuration protocol
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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f52b5d5b4c
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use error code in read_arch command
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2020-06-11 19:31:07 -06:00 |