tangxifan
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1a8968cb37
|
now FPGA-SDC will constrain timing for routing tracks using the VPR Rmetal parameter in ARCH XML
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2020-04-20 21:12:51 -06:00 |
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tangxifan
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9761d13eef
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update microbenchmark and2 module name
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2020-04-20 13:37:39 -06:00 |
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tangxifan
|
f06f2d72be
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deploy single mode in regression tests
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2020-04-20 13:16:52 -06:00 |
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tangxifan
|
489ca75230
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adapt benchmark and_latch module name to be different than benchmark and
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2020-04-20 13:15:05 -06:00 |
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tangxifan
|
f6b7583a2a
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add tasks for single mode
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2020-04-20 12:55:40 -06:00 |
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tangxifan
|
8b03ec900f
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fine-tune micro benchmark to fit port mapping in testbenches
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2020-04-19 17:05:12 -06:00 |
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tangxifan
|
e10cafe0a5
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Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
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2020-04-19 16:42:31 -06:00 |
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tangxifan
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32ed609238
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update micro benchmark set and regression tests using them
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2020-04-19 12:49:07 -06:00 |
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tangxifan
|
98878f474b
|
light change on arch file to accelerate mcnc big20 run
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2020-04-19 12:03:31 -06:00 |
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tangxifan
|
cc163081f5
|
recover mcnc big20 test configuration
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2020-04-18 21:06:43 -06:00 |
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tangxifan
|
2e3a811f4f
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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
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2020-04-18 21:04:46 -06:00 |
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tangxifan
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f76a3090c4
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add mcnc big20 test cases and start debugging
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2020-04-18 19:25:16 -06:00 |
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tangxifan
|
95863e996a
|
minor update on arch to use auto layout sizing
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2020-04-18 18:43:56 -06:00 |
|
tangxifan
|
2f3a36ee81
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update timing and rename the arch file
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2020-04-18 18:39:47 -06:00 |
|
tangxifan
|
7ce34be175
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update sample architecture timing
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2020-04-17 22:06:06 -06:00 |
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tangxifan
|
2ea4b8a2a2
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add more flagship architectures
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2020-04-17 19:12:27 -06:00 |
ganeshgore
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7e7001e993
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-15 20:56:13 -06:00 |
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tangxifan
|
a7d900088b
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now generating simulation ini file will try to create directory first
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2020-04-15 20:53:37 -06:00 |
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tangxifan
|
72e8824a87
|
bug fixed on removing undriven pins (direct connection between clbs) from cb
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2020-04-15 20:41:15 -06:00 |
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tangxifan
|
2ffd174e6a
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fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
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2020-04-15 15:48:33 -06:00 |
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tangxifan
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032ebc29e6
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Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2020-04-15 12:53:20 -06:00 |
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tangxifan
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1e742a3676
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add test case on auto-check test benches
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2020-04-15 12:52:52 -06:00 |
|
ganeshgore
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689c4a3e19
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BugFix: The filename in the previous commit
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2020-04-15 12:44:22 -06:00 |
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tangxifan
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46fe1e84ce
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Merge branch 'dev' into ganesh_dev
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2020-04-15 12:27:51 -06:00 |
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ganeshgore
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7f37bf1441
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Added formal verification support to fpga_flow script
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2020-04-15 12:24:51 -06:00 |
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tangxifan
|
56e0d2a918
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critical patch on the ccff head and tail connection in grid modules for VPR7+OpenFPGA
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2020-04-13 12:58:44 -06:00 |
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tangxifan
|
07a384e440
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now use openfpga tokenizer to trim command line string in openfpga shell
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2020-04-13 11:08:31 -06:00 |
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tangxifan
|
7ba3e27371
|
add duplicated_grid_pin test case to Travis CI
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2020-04-12 20:10:51 -06:00 |
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tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
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2020-04-12 20:06:40 -06:00 |
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tangxifan
|
59ea0a6ad5
|
add implicit verilog test case to Travis CI
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2020-04-12 20:00:20 -06:00 |
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tangxifan
|
23aef96d3a
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add behavioral verilog test case to Travis CI
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2020-04-12 19:55:47 -06:00 |
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tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
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2020-04-12 19:07:53 -06:00 |
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tangxifan
|
a614e5aad9
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add long adder chain to Travis CI
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2020-04-12 15:43:19 -06:00 |
|
tangxifan
|
f71a85a1d4
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add test cases on different routing multiplexer circuit designs to Travis CI
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2020-04-12 15:39:45 -06:00 |
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tangxifan
|
214d98fbcd
|
add register chain and scan chain to Travis CI
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2020-04-12 15:28:22 -06:00 |
|
tangxifan
|
148cc74d6a
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add io test cases to Travis CI
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2020-04-12 15:01:47 -06:00 |
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tangxifan
|
da5af8f0e0
|
try to add aib test case. bug found
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2020-04-12 14:54:45 -06:00 |
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tangxifan
|
28cb412359
|
add test case of wide BRAM 16k to Travis CI
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2020-04-12 14:37:08 -06:00 |
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tangxifan
|
5d665aa04b
|
reshape bram test case
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2020-04-12 14:32:09 -06:00 |
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tangxifan
|
600a48edc7
|
add test case of BRAM to Travis CI
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2020-04-12 14:27:05 -06:00 |
|
tangxifan
|
2444752de8
|
add untileable test case to Travis CI
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2020-04-12 14:08:24 -06:00 |
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tangxifan
|
cc7adae91e
|
deploy openfpga shell in Travis CI
|
2020-04-12 12:57:13 -06:00 |
|
tangxifan
|
d806ad3148
|
add testcases using openfpga_shell in openfpga_flow
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2020-04-12 12:54:21 -06:00 |
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tangxifan
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68fd296e14
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add more test vpr architecture to regression tests
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2020-04-12 12:49:16 -06:00 |
|
ganeshgore
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80bdb41df6
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Updated task file to run formal verification
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2020-04-11 18:30:21 -06:00 |
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ganeshgore
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e6de0cdce0
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Merge remote-tracking branch 'lnis_origin/dev' into ganesh_dev
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2020-04-11 18:05:31 -06:00 |
|
tangxifan
|
49ddbf98c3
|
add more testing architecture to openfpga_flow
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2020-04-11 18:01:09 -06:00 |
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tangxifan
|
130b78ca74
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update arch in openfpga_flow
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2020-04-11 18:00:37 -06:00 |
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tangxifan
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c67a480d6f
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Merge branch 'ganesh_dev' into dev
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2020-04-11 16:48:56 -06:00 |
|
ganeshgore
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f6b3c5854a
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Bugfix :
+ OpenFPGA template variables update
+ Default path for the verilog netlist
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2020-04-11 16:45:22 -06:00 |