035043d0d8
[Script] Revert to the state that post synthesis verilog is not required for yosys_vpr
2021-03-10 13:36:11 -07:00
5d46537b5b
[Script] Allow users to specify custom post-synthesis verilog for simulation
2021-03-10 11:45:55 -07:00
aafd87c3f9
[Flow] Update flow-run to support custom yosys rewrite scripts
2021-03-10 11:36:29 -07:00
67cd9a69b7
[Flow] Extended yosys variable subtitution
2021-03-08 00:21:07 -07:00
2344cdcabc
merge
2021-02-08 21:11:28 -05:00
df4a397470
[Cleanup] Removed deadcode
2021-02-03 10:35:14 -07:00
0b82b6439b
[Regression] Upgraded runtime enviroment to python3.8
2021-01-26 16:40:45 -07:00
1554f583b7
[Flow] Now support explicit variable file for task
2020-11-25 17:22:41 -07:00
45af056304
TASK_NAME and TASK_DIR variables are avaialble in config file now
2020-07-27 14:14:57 -06:00
0e46e0d857
Updated task.conf format to have transparent shell variables
2020-07-27 14:08:58 -06:00
41585436c8
Added external_fabric_key_file key
2020-06-12 15:37:12 -06:00
c1b73efa62
Added support for simulation setting file in the task flow
2020-06-10 23:12:30 -06:00
ea4122a8a4
Updated openfpga_flow and task file to support sheel run
2020-04-06 00:34:36 -06:00
6bb11918dc
Updated modelsim and collected result
2019-11-16 19:10:04 -07:00
595d2d3070
Simple argument shuffle
2019-11-01 18:21:26 -06:00
50039a4b6e
Added remove run directory option
2019-09-21 23:35:56 -06:00
e5c99c8b12
Quick terminate on fail added
2019-09-13 23:56:38 -06:00
bd9e57bc37
Added better task name
2019-09-13 23:30:42 -06:00
a6e592247e
Replaced options exit_on fail and show_thread logs
2019-09-13 22:50:20 -06:00
bcbcd463fe
Added pending runs in log
2019-09-06 11:48:13 -04:00
48ec1eefcd
Added fpga_task cmd options in doc [ci skip]
2019-09-02 02:45:05 -06:00
241b001282
Added openfpga_task doc
2019-09-01 22:15:53 -06:00
ad4c688206
Added print for JobID to architecture mapping
2019-08-31 22:04:57 -06:00
02137805c7
Added python version check in flow and task scripts
2019-08-29 22:14:30 -06:00
a25124b58c
Added additional PATH variables
2019-08-29 21:37:07 -06:00
f54a8522fa
Log prints task stats
2019-08-27 22:04:32 -06:00
715adc13ff
Failed result do not throw error
2019-08-27 21:25:38 -06:00
632c9d6976
Added python execution path in config file
2019-08-25 00:42:48 -06:00
f558437ae1
Added task for vpr_blif flow
2019-08-25 00:23:39 -06:00
6e7de16ad4
Solved bug in commnad rearrangement
2019-08-22 23:41:25 -06:00
d5ce1b557e
Made thread logs prettier
2019-08-22 16:56:58 -06:00
764d7039b5
Import utils bug fixing for travis test
2019-08-21 12:42:58 -06:00
e51ff44710
Added execution time information in logs
2019-08-21 11:08:47 -06:00
a335a57c6c
Added debug option to commnad line arguments
2019-08-21 11:08:13 -06:00
b7484ef178
Removed traces of old template file
2019-08-20 15:58:19 -06:00
7f6c1b3e00
Code re-arrangement
...
+ Added support for subdirectory task in openfpga_task
+ Rearranged function order
+ Combined vpr re-route and standrad run function
+ Removed external_call function from fpga_flow script
+ Added .gitignore to task directory
2019-08-18 12:26:05 -06:00
c43c3cdf25
Added VPR output parse option
2019-08-16 13:36:39 -06:00
effbd332aa
Added task report generation
2019-08-16 10:59:44 -06:00
901932a4fc
First draft: Working openfpga task flow
2019-08-16 09:44:50 -06:00
5d3708651e
Added fpga_flow and fpga_task script
...
+ Missed local intermediate commits
2019-08-15 14:39:58 -06:00
b82369dd96
Added first draft of fpga_task script
2019-08-09 00:17:06 -06:00
tangxifan
Ganesh Gore
Nachiket Kapre