tangxifan
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19a551e641
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[Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region
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2021-10-09 16:44:04 -07:00 |
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tangxifan
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8f5f30792f
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[Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface
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2021-10-08 15:25:37 -07:00 |
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tangxifan
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b87b7a99c5
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[Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators
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2021-09-29 20:21:46 -07:00 |
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tangxifan
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be4c850d2d
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[Engine] Split the function to add BL/WL configuration bus connections for support flatten BL/WLs
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2021-09-24 12:03:35 -07:00 |
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tangxifan
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ed80d6b3f4
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[Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier
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2021-09-05 13:23:38 -07:00 |
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tangxifan
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cf2e479d18
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[Engine] Refactor the TopModuleNumConfigBits data structure
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2021-09-05 12:01:38 -07:00 |
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tangxifan
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5759f5f35b
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[Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder
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2021-09-03 17:55:23 -07:00 |
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tangxifan
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088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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tangxifan
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448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
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bd49ea95d4
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[Tool] Add function to comput configuration bits by region
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2020-10-28 12:37:09 -06:00 |
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tangxifan
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f93d46a870
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[OpenFPGA Tool] Add multiple configuration chain support in top module builder
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2020-09-28 19:03:19 -06:00 |
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tangxifan
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552dddffd0
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[OpenFPGA Tool] Support configurable regions in module manager
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2020-09-28 18:13:07 -06:00 |
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tangxifan
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a5055e9d26
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add support about loading external fabric key
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2020-06-12 13:03:11 -06:00 |
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tangxifan
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9dbf536306
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add shuffled configurable children support for top module
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2020-06-12 11:16:53 -06:00 |
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tangxifan
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5368485bd6
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keep bug fixing for memory bank configuration protocol. Reduce number of BL/WLs at the top-level
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2020-06-11 19:31:14 -06:00 |
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tangxifan
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fa8dfc1fbd
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add configuration protocol ports to top module for memory bank organization
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2020-06-11 19:31:13 -06:00 |
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tangxifan
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ed2325ec9e
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add frame decoder build-up to top-level module
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2020-06-11 19:31:09 -06:00 |
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tangxifan
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c855ab24f5
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put build top module memory connections online
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2020-02-14 11:07:04 -07:00 |