bc34efe337
[Arch] Bug fix in the architecture using BRAM spanning two columns
2021-04-28 14:32:17 -06:00
be98775ae5
[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
2021-04-28 10:45:10 -06:00
79b27a6329
[Arch] Patch arch using DPRAM block with wide = 2
2021-04-28 10:29:09 -06:00
834657f2da
[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
2021-04-27 23:41:14 -06:00
0f8aaae2bc
[Arch] Patch architecture using 16kbit dual port RAM
2021-04-27 19:54:34 -06:00
8c007c7c49
[Arch] Add a new example architecture where a DSP block occupies a 2x2 grid
2021-04-26 16:28:10 -06:00
7d4c5e3cd1
[Arch] Patch pin location of dsp8 to be evenly placed on the right side of a height=2 block
2021-04-26 12:00:57 -06:00
6e87b8875b
[Arch] Patch the pin location of frac dsp16 to appear on the top side of a height=2 block
2021-04-26 11:59:25 -06:00
5adffad602
[Arch] Changes to the arch to avoid a bug where the rr_nodes at top side of a heterogenenous block have no fan-in!!!
2021-04-24 15:49:53 -06:00
4f454abfde
[Arch] Add a new architecture using fracturable 16-bit DSP blocks
2021-04-24 14:01:42 -06:00
ce6018e123
[Arch] Enriched DFF model to support active-low/high FFs
2021-04-21 22:48:31 -06:00
9d9840d9b7
[Arch] Add architecture using multi-mode DFFs
2021-04-21 19:49:48 -06:00
e3dafe99da
[Arch] Revert to old version arch due to editing by mistake
2021-04-16 20:58:32 -06:00
16e02ef485
[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
2021-04-16 20:47:39 -06:00
4239bb4e68
[Arch] Patch architecture files using multi-mode DFFs
2021-04-16 19:59:55 -06:00
f2f7f010ea
[Arch] Add new architectures using DFF with reset in VPR
2021-04-16 19:26:18 -06:00
64294ae4eb
[Doc] Update README for architecture files due to new architecture features
2021-04-16 19:25:54 -06:00
44d97ead86
Merge branch 'master' into hetergeneous_arch
2021-03-23 17:05:03 -06:00
fdec72b5bc
[Arch] Add an example architecture with 8-bit single-mode multiplier
2021-03-23 15:35:06 -06:00
911979a731
[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
2021-03-20 18:04:59 -06:00
910f8471dd
[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
2021-03-17 15:10:05 -06:00
ad25944e59
[Arch] Patched superLUT architecture example when trying adder8 synthesis script
2021-02-23 19:00:27 -07:00
ca135f3325
[Arch] Add flagship architecture with 8-clock
2021-02-22 15:01:18 -07:00
1c09c55e9f
[Arch] Add hetergenenous 8-clock FPGA architecture
2021-02-22 13:38:50 -07:00
0ac75723af
[Arch] Add new architecture with 8 clocks
2021-02-22 11:00:45 -07:00
b9c2564a7e
[Arch] Add VPR architecture with 5 clocks to test counter with 5 clocks
2021-02-22 10:49:21 -07:00
7dcc14d73f
[Arch] Bug fix in the example arch with super LUT
2021-02-09 15:52:22 -07:00
304b26c97f
[Arch] Add example architectures for superLUT circuit model
2021-02-09 15:11:12 -07:00
00fc3d7622
Merge pull request #217 from lnis-uofu/dev
...
Synchronize the out-of-date XML syntax 'disable_in_pack' with VPR upstream
2021-02-05 09:53:28 -07:00
dc09c47411
[Arch] Remove packable from architecture files and replace with disable_packing
2021-02-04 18:03:56 -07:00
66bc370c4d
[Arch] Use disable_packing in architecture library
2021-02-04 16:29:03 -07:00
a4c266d59a
[Arch] Add pack patterns for soft adders; Still fail in packing
2021-02-03 19:11:15 -07:00
cac1160bf7
[Arch] Patch QLSOFA architecture to support carry chain pattern; Still buggy for VPR packer; Looking for a solution
2021-02-03 11:20:56 -07:00
021520783b
[Arch] Add dummy timing info to adder_lut4 and carry_follower model
2021-02-02 15:49:43 -07:00
10302752a7
[Arch] Bug fix in architecture. Now soft adder modes are accepted
2021-02-01 13:43:39 -07:00
d8927e12e8
[Arch] Add soft adder operating mode to test architecture
2021-02-01 12:25:37 -07:00
9bbf214456
[Arch] Update the caravel architecture
2021-01-29 17:00:17 -07:00
3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases ( #200 )
...
* Add required files for LUTRAM integration and testing
* Add task for lutram
* Repair format (tab and space mismatched)
* Add disclaimer in architecture file
Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
2021-01-29 10:19:05 -07:00
16b4e89326
[Doc] Update documentation for VPR architectures
2021-01-12 17:57:40 -07:00
7ccdff4543
[Arch] Add an architecture using 4 clocks
2021-01-12 17:55:57 -07:00
aaf582acc5
[Arch] Bug fix
2021-01-10 11:05:57 -07:00
f21d22f691
[Doc] Update README for new architectures
2021-01-10 10:54:59 -07:00
853e7b1a40
[Arch] Add vpr architecture where I/O can be either combinational or registered
2021-01-10 10:54:09 -07:00
891e2f8aa3
Adding arch xml from SOFA repo. Also updating the script with its file location
2020-12-16 04:14:18 -08:00
6001da3a40
[Arch] Bug fix in tileable I/O arch example
2020-12-04 17:56:54 -07:00
1d0bdcfeca
[Arch] Simplify the grid layout modeling
2020-12-04 17:38:44 -07:00
1c3f625e41
[Arch] Force empty tiles at corners for tileable I/O arch example
2020-12-04 17:11:06 -07:00
186eb0f0a4
[Arch] Add tileable I/O architecture example
2020-12-04 15:59:39 -07:00
7a0a3398d4
[Arch] Add new architecture to test global reset ports defined thru tile ports
2020-11-30 17:43:41 -07:00
a60bd4d14a
[Arch] Bug fix in nature fracturable architecture
2020-11-25 22:48:26 -07:00
tangxifan
AurelienAlacchi
Lalit Sharma