tangxifan
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6e1d49d74e
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start to support direct mapping to MUX2 standard cells
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2019-07-17 07:54:23 -06:00 |
AurelienUoU
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19ccbce9d0
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Rename option to use circuit_model rather than spice_model
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2019-07-12 16:18:28 -06:00 |
Baudouin Chauviere
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4ca0967453
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Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
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2019-07-09 14:35:51 -06:00 |
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Baudouin Chauviere
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25f5bc7792
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Latest version, not stable yet but close
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2019-07-09 08:34:01 -06:00 |
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tangxifan
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3077efa74f
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add option to compact tileable routing arch
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2019-07-04 17:13:34 -06:00 |
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tangxifan
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95674c4687
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added Switch Block SubType and SubFs for tileable rr_graph generation
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2019-07-02 10:00:02 -06:00 |
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tangxifan
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548242b368
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plug-in tileable rr generator which can be enable by a XML property
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2019-06-20 21:06:26 -06:00 |
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tangxifan
|
f43955037c
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remove input port requirements for SRAM circuit module
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2019-06-10 15:29:44 -06:00 |
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tangxifan
|
f5b6ee6adf
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update travis configuration and clean up repository
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2019-06-07 22:19:11 -06:00 |
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tangxifan
|
8c5ec4572d
|
revert string to sprintf
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2019-06-07 20:20:41 -06:00 |
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tangxifan
|
eef1312325
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updated bitstream to use new RRSwitchBlock as well as the report timing engine
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2019-05-24 12:54:10 -06:00 |
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tangxifan
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ea8c36ce6e
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upgrade Verilog SB generator using the RRSwitchBlock
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2019-05-23 17:37:39 -06:00 |
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tangxifan
|
502344b13a
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add missing files
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2019-05-22 12:35:12 -06:00 |
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tangxifan
|
efbc454cdd
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Add Class for RRSwtichBlock and plug-in to replace the old t_sb
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2019-05-22 12:34:06 -06:00 |
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tangxifan
|
b185a17359
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add routing_channel unique module generation
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2019-05-20 22:33:17 -06:00 |
BaudouinChauviere
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cd4dc8b2e8
|
Delete read_xml_arch_file.c
Already present in SRC
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2019-05-06 12:55:18 -06:00 |
|
Baudouin Chauviere
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a5a1a376ab
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Modified code for cleaner delay naming convention
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2019-05-06 12:52:49 -06:00 |
|
Baudouin Chauviere
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e7b1d89985
|
Change syntax name for loop_breaker_delay_before/after which is more explicit
|
2019-05-06 12:25:26 -06:00 |
|
Baudouin Chauviere
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7c257ebda7
|
Fix on the makefile which was not targetting the right folder
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2019-05-06 12:21:53 -06:00 |
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tangxifan
|
6e6ae1cc3d
|
fixed bugs in CMakeLists.txt and Makefile
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2019-05-03 23:03:04 -06:00 |
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tangxifan
|
4e3487b691
|
Add latest abc and update ace dependence
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2019-05-03 18:56:03 -06:00 |
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tangxifan
|
70b66e0799
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 14:22:20 -06:00 |
|
Baudouin Chauviere
|
7860042276
|
added before after loop breaker constraining
|
2019-05-03 14:00:06 -06:00 |
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tangxifan
|
11cf30b239
|
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
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2019-05-03 11:54:35 -06:00 |
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tangxifan
|
5a97e3e602
|
update Makefile t
|
2019-05-03 11:48:41 -06:00 |
|
Baudouin Chauviere
|
921b694400
|
Bug fix sdc breaking loop of edges outside current interconnect
|
2019-05-03 10:42:35 -06:00 |
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tangxifan
|
c46c0fc97d
|
bug fixing for SDC generator
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2019-04-26 14:07:44 -06:00 |
|
tangxifan
|
46d44fa42a
|
Update VPR7 X2P with new engine
|
2019-04-26 12:23:47 -06:00 |
|
Aur??Lien ALACCHI
|
8ac566ecc0
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Add timing and initialization for simulation
|
2018-12-04 17:32:09 -07:00 |
Aurelien Alacchi
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e0c2fc2c8a
|
Documentation_code&example_update
|
2018-10-12 15:50:09 -06:00 |
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tangxifan
|
d683134b12
|
rename customized vpr7 to vpr7 XML to Production
|
2018-09-17 23:10:45 -06:00 |