tangxifan
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aebf7453d0
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[Arch] Add architecture files with compatible I/O capacity with caravel SoC
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2020-11-04 16:57:00 -07:00 |
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tangxifan
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61376a2979
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[Test] Add test cases for various tile organization
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2020-11-04 16:32:52 -07:00 |
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tangxifan
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cf455df555
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[Arch] Add architecture for bottom-right and top-left tile organization
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2020-11-04 16:24:36 -07:00 |
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tangxifan
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46ca406f10
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[Arch] Add a new vpr architecture with new tile organization
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2020-11-04 16:20:01 -07:00 |
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tangxifan
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049ca14461
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[Doc] Add new naming rules for vpr architecture files
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2020-11-04 16:17:56 -07:00 |
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tangxifan
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c036c87d6d
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[HDL] Bug fix in the GP output pad
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2020-11-02 18:37:53 -07:00 |
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tangxifan
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3b49e6d090
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[Arch] Patch embedded IO architecture by forcing only 1 pad per block
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2020-11-02 15:39:31 -07:00 |
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tangxifan
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c512644a09
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[Arch] Patch embedded I/O example architecture
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2020-11-02 15:16:19 -07:00 |
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tangxifan
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7e9e0ec9d4
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[HDL] Bug fix in I/O HDL code
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2020-11-02 15:15:45 -07:00 |
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tangxifan
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2f237a6240
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[HDL] Add HDL codes for embedded I/Os
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2020-11-02 14:01:27 -07:00 |
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tangxifan
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55b77ac6cb
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[Arch] Bug fixed in embedded FPGA architecture
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2020-11-02 13:57:15 -07:00 |
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tangxifan
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a7e7fa2005
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[Arch] Update arch with true embedded I/O definition
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2020-11-02 13:29:40 -07:00 |
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tangxifan
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65ca53ac98
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[Test] Update test case with the new arch name
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2020-11-02 13:16:42 -07:00 |
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tangxifan
|
8c8190047f
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[Arch] Rename architecture files for embedded I/Os
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2020-11-02 13:15:19 -07:00 |
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tangxifan
|
bc00dee858
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[Test] Add test case for embedded I/O
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2020-11-02 12:28:25 -07:00 |
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tangxifan
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f86f43d287
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[Arch] Add openfpga architecture file for constrained pin equivalence
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2020-11-02 12:27:40 -07:00 |
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tangxifan
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795b30f76b
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[Arch] Add VPR architecture with partial pin equivalence
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2020-11-02 11:54:25 -07:00 |
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tangxifan
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4c14428400
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[Test] Add test case for fast configuration support on multi-region frame-based configuration protocol
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2020-10-30 10:50:00 -06:00 |
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tangxifan
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ca7d43275d
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[Test] Add test case for multi_region configuration frame
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2020-10-30 10:48:29 -06:00 |
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tangxifan
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29da368742
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[Arch] Add architecture example for multi-region frame-based architecture using both set/reset for configurable memories
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2020-10-30 10:46:47 -06:00 |
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tangxifan
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b701bd2640
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[Arch] Add multi-region architecture example for frame-based protocol
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2020-10-30 10:45:14 -06:00 |
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tangxifan
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1d930d1b5d
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[Architecture] Add missing arch files and bug fix
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2020-10-29 18:08:26 -06:00 |
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tangxifan
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153b265a6d
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[Architecture] Add openfpga architecture using multiple memory banks whose memory cell has both reset and set
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2020-10-29 16:32:05 -06:00 |
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tangxifan
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241ebf054a
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[Test] Add a test case for validating fast configuration techniques on multi-region memory banks
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2020-10-29 16:29:46 -06:00 |
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tangxifan
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ff386001c4
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[Test] Add openfpga task for multi-region memory banks
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2020-10-29 13:56:32 -06:00 |
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tangxifan
|
7534474423
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[Arch] Add architecture for multiple-region memory banks
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2020-10-29 13:54:51 -06:00 |
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tangxifan
|
179ae355d0
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[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
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2020-10-13 12:02:26 -06:00 |
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tangxifan
|
97c3bf7ea0
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[Test] Add a test case for non-constant input multiplexers
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2020-10-13 11:58:17 -06:00 |
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tangxifan
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c5bcd93408
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[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
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2020-10-13 11:57:21 -06:00 |
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tangxifan
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99b1e68d92
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[Architecture] Add architecture using GND as constant inputs for multiplexers
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2020-10-13 11:39:27 -06:00 |
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tangxifan
|
570b494df7
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[Test] Add test case for using GND signal as constant input for routing multiplexers
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2020-10-13 11:38:54 -06:00 |
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tangxifan
|
dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
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e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
|
8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
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9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
|
e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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tangxifan
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82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
|
d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
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d4d02ab16a
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[Regression Test] Move fabric key tests to basic tests
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2020-09-29 14:22:23 -06:00 |
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tangxifan
|
ff6570df9d
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[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
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2020-09-29 14:19:40 -06:00 |
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tangxifan
|
4f00d310d3
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[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
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tangxifan
|
02ea639959
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[Regression Test] Add test for fabric key based on multiple region
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2020-09-29 14:13:38 -06:00 |
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tangxifan
|
a0d1d68402
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[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
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2020-09-29 13:53:41 -06:00 |
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tangxifan
|
d5c7411399
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[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
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2020-09-29 13:50:31 -06:00 |
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tangxifan
|
5be5835b71
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[Regression Test] Add multiple region configuration chain test case
|
2020-09-29 13:48:39 -06:00 |
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tangxifan
|
23449dc5c3
|
[Architecture] Add multiple region configuration chain architecture
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2020-09-29 13:46:40 -06:00 |
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tangxifan
|
e09e5fa6c6
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[Architecture] Update fabric key for region syntax
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2020-09-27 20:40:37 -06:00 |
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tangxifan
|
ffd926d686
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[Architecture] Update external bitstream
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2020-09-25 21:30:59 -06:00 |
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tangxifan
|
dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
|
019208ec0f
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[Architecture] Reorganize the cell netlists and update architecture files accordingly
|
2020-09-25 11:55:28 -06:00 |