tangxifan
|
707300a6e4
|
[Architecture] Bug fix for using both reset and set architecture
|
2020-09-23 22:07:40 -06:00 |
|
tangxifan
|
77a1f99564
|
[Architecture] Bug fix for architecture using set only
|
2020-09-23 22:04:24 -06:00 |
|
tangxifan
|
fcf1ff418f
|
[Architecture] Add Verilog for SRAM using set/reset
|
2020-09-23 21:53:38 -06:00 |
|
tangxifan
|
73e59d67af
|
[Architecture] Add test case for fast configuration using set signals
|
2020-09-23 21:50:23 -06:00 |
|
tangxifan
|
349aa79069
|
[Regression test] Add test case for smart fast configuration
|
2020-09-23 21:49:38 -06:00 |
|
tangxifan
|
9331ef941d
|
[Architecture] Add architecture that use both set and reset signals
|
2020-09-23 21:46:04 -06:00 |
|
tangxifan
|
7591060fbd
|
[Architecture] Add configurable latch Verilog designs and assoicated architectures
|
2020-09-23 21:45:06 -06:00 |
|
tangxifan
|
8fa4fa1125
|
[Architecture] Add openfpga architecture using set signals for configurable latch
|
2020-09-23 21:39:31 -06:00 |
|
tangxifan
|
05c2e652a4
|
[Regression Test] Add a new test case for using scan-chain ff in frame-based configuration protocol
|
2020-09-23 20:44:06 -06:00 |
|
tangxifan
|
2869eae8a9
|
[Architecture] Add openfpga architecture where scan-chain ff is used in frame-based configuration protocol
|
2020-09-23 20:43:15 -06:00 |
|
tangxifan
|
fc60b18191
|
[Architecture] Now a regular flip-flop can be used in frame-based configuration
|
2020-09-23 20:41:49 -06:00 |
|
tangxifan
|
8e4e66038a
|
[Architecture] Bug fix for standalone memory
|
2020-09-23 19:32:48 -06:00 |
|
tangxifan
|
129caea38c
|
[Architecture] Patch configurable latch Verilog HDL with resetb
|
2020-09-23 18:30:48 -06:00 |
|
tangxifan
|
1864b080a2
|
[Architecture] Bug fix in configurable latch Verilog HDL
|
2020-09-23 18:28:45 -06:00 |
|
tangxifan
|
ebb866d04a
|
[Architecture] Patch frame based using ccff
|
2020-09-23 18:04:14 -06:00 |
|
tangxifan
|
906191e931
|
[Architecture] Use strict latch Verilog HDL in frame-based procotol
|
2020-09-23 17:58:13 -06:00 |
|
tangxifan
|
645db17168
|
[Architecture] Patch DFF Verilog HDL
|
2020-09-23 17:52:59 -06:00 |
|
tangxifan
|
092ada39f4
|
[Architecture] Add Verilog HDL for DFF with write enable
|
2020-09-23 17:49:30 -06:00 |
|
tangxifan
|
ad385c6d69
|
[Regression Test] Add test case for using SRAM cell in frame-based configuration
|
2020-09-23 17:39:36 -06:00 |
|
tangxifan
|
1a2c66f07d
|
[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
|
2020-09-23 17:34:49 -06:00 |
|
tangxifan
|
a3c982a83f
|
[Architecture] Patch the openfpga architecture using active-low configurable latch
|
2020-09-23 17:27:16 -06:00 |
|
tangxifan
|
f23c25e123
|
[Regression Test] Add test case for configurable latch with active-low reset
|
2020-09-23 17:25:17 -06:00 |
|
tangxifan
|
a94c2655c2
|
[Architecture] Patch Verilog HDL for configurable latch
|
2020-09-23 17:21:30 -06:00 |
|
tangxifan
|
893859be37
|
[Architecture] Add openfpga architecture using active-low configurable latch
|
2020-09-23 17:21:00 -06:00 |
|
tangxifan
|
b242ab79bd
|
[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset
|
2020-09-23 17:19:02 -06:00 |
|
tangxifan
|
149d5b20bd
|
[Regression Test] Add test case for fixed device support
|
2020-09-23 16:47:11 -06:00 |
|
tangxifan
|
c92cf71891
|
[Regression Test] Add a new template script for fixed device support
|
2020-09-23 16:46:41 -06:00 |
|
tangxifan
|
3350695806
|
[Regression test] Add test case for pattern based local routing architecture
|
2020-09-23 16:06:47 -06:00 |
|
tangxifan
|
1aab691e9d
|
[Architecture] Add openfpga architecture using pattern based local routing
|
2020-09-23 16:06:16 -06:00 |
|
tangxifan
|
951a47b19c
|
[Architecture] Add k4 series architecture using pattern-based local routing
|
2020-09-23 16:05:39 -06:00 |
|
tangxifan
|
7729f671ab
|
[Regression Tests] Remove deadlink
|
2020-09-22 18:35:41 -06:00 |
|
tangxifan
|
51c0319657
|
[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
|
2020-09-22 15:32:54 -06:00 |
|
tangxifan
|
70b8b02f74
|
[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
|
2020-09-22 15:32:11 -06:00 |
|
tangxifan
|
72749be4bd
|
[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
|
2020-09-22 15:31:34 -06:00 |
|
tangxifan
|
61bcbaafd8
|
[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
|
2020-09-22 15:15:19 -06:00 |
|
tangxifan
|
3d1f49fb2f
|
[Regression Test] Add testcase for k4n4 with multiple segments
|
2020-09-22 12:47:41 -06:00 |
|
tangxifan
|
13df6c1c21
|
[Architecture] Add openfpga architecture for k4n4 using multiple segments
|
2020-09-22 12:36:11 -06:00 |
|
tangxifan
|
8a3934b749
|
[Architecture Add vpr architecture for k4n4 using multiple wire segments
|
2020-09-22 12:35:39 -06:00 |
|
tangxifan
|
5741664580
|
[Regression Test] Add test case for k4n4 bram architecture
|
2020-09-22 12:23:56 -06:00 |
|
tangxifan
|
ddf999b6b9
|
[Architecture] Add verilog HDL for dual-port BRAM 1k
|
2020-09-22 12:23:28 -06:00 |
|
tangxifan
|
26fba4a94b
|
[Architecture] Add openfpga architectue for k4n4 with bram blocks
|
2020-09-22 12:22:59 -06:00 |
|
tangxifan
|
daf776b7b1
|
[Architecture] Add k4n4 architecture with bram block for basic tests
|
2020-09-22 12:22:32 -06:00 |
|
tangxifan
|
3bf94b8e34
|
[Regression test] Remove no local routing from fpga verilog tests
|
2020-09-22 11:48:19 -06:00 |
|
tangxifan
|
7ed9f76b06
|
[Regression test] Move k4n4 no local routing to basic test
|
2020-09-22 11:47:03 -06:00 |
|
tangxifan
|
2dea97afb6
|
[Regression test] reduce runtime for k4n4 test in basic testing
|
2020-09-22 11:45:29 -06:00 |
|
tangxifan
|
ea4dd410b7
|
[Regression Test] Add k4n4 fracturable lut test case to basic test
|
2020-09-22 11:41:36 -06:00 |
|
tangxifan
|
dad19cac9a
|
[Regression test] Add k4 series architecture: fracturable adder
|
2020-09-22 11:39:18 -06:00 |
|
tangxifan
|
dd192a2f54
|
[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
|
2020-09-22 11:34:23 -06:00 |
|
tangxifan
|
7a6f5a06f7
|
[Architecture] Add a k4n4 architecture with carry chain to quick test
|
2020-09-22 11:33:56 -06:00 |
|
tangxifan
|
aa5f5fc7e0
|
[Architecture] Bring back pin equivalence for no local routing architecture
|
2020-09-21 22:22:39 -06:00 |
|
tangxifan
|
a8a269aa82
|
[Architecture] Temporary patch for the no local routing architecture
|
2020-09-21 19:51:23 -06:00 |
|
tangxifan
|
acf318f184
|
[Regression test] Bug fix in test case fabric_chain
|
2020-09-21 18:58:35 -06:00 |
|
tangxifan
|
e4291eb27e
|
[Regression Tests] Now use fixed device layout in test cases for best coverage
|
2020-09-21 18:44:13 -06:00 |
|
tangxifan
|
7a57cc9cf4
|
[Architecture] A new device layout to k4n4 to test untileable architecture
|
2020-09-21 18:36:50 -06:00 |
|
tangxifan
|
2bbfcb5753
|
[Architecture] Add a new device layout to k4n4 for testing tileable routing
|
2020-09-21 18:34:31 -06:00 |
|
tangxifan
|
e1c5947143
|
[Architecture] Add auto layout and fixed layout to architectures
|
2020-09-21 18:01:51 -06:00 |
|
tangxifan
|
936a164eee
|
[OpenFPGA flow] Add a new template script to use a fixed device layout
|
2020-09-21 17:48:28 -06:00 |
|
tangxifan
|
d7f8b3abad
|
[Architecture] Add k4 N4 untilable architecture
|
2020-09-21 17:44:37 -06:00 |
|
tangxifan
|
a83bc3f75c
|
[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
|
2020-09-21 17:38:16 -06:00 |
|
tangxifan
|
e9c0e90544
|
[Architecture] Add a VPR architectue using fracturable LUT4
|
2020-09-21 17:37:26 -06:00 |
|
tangxifan
|
60f328a2ab
|
[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
|
2020-09-21 17:36:57 -06:00 |
|
tangxifan
|
681e80d4b6
|
[Regression tests] update frac_lut test case using more representative benchmarks
|
2020-09-17 10:39:22 -06:00 |
|
tangxifan
|
367cf59efd
|
[Benchmark] Bug fix in the and2_or2 benchmark
|
2020-09-17 10:35:13 -06:00 |
|
tangxifan
|
de48b8c7b2
|
[Benchmark] Add a new micro benchmark to test fracturable LUTs
|
2020-09-17 10:21:25 -06:00 |
|
tangxifan
|
ca1bafc688
|
[OpenFPGA Architecture] Add full pin equivalence to full output crossbar architecture
|
2020-09-16 19:26:12 -06:00 |
|
tangxifan
|
c22d8e2421
|
[Architecture] Bug fix in no local routing architecture
|
2020-09-16 18:07:52 -06:00 |
|
tangxifan
|
c40c9f5876
|
[Regression test] add test case for no local routing architecture
|
2020-09-16 18:05:33 -06:00 |
|
tangxifan
|
f5b7ac6269
|
[OpenFPGA Architecture] Add a new architecture with no local routing
|
2020-09-16 18:04:55 -06:00 |
|
tangxifan
|
35d47ee0e7
|
[Regression tests] bug fix in the test case for fully connected output crossbar
|
2020-09-16 17:33:54 -06:00 |
|
tangxifan
|
030d7f02f8
|
[OpenFPGA architecture] bug fix in the fully connected output crossbar architecture
|
2020-09-16 17:30:08 -06:00 |
|
tangxifan
|
30fb99095f
|
[Regression Tests] Add new test case for fully connected output crossbar
|
2020-09-16 17:29:15 -06:00 |
|
tangxifan
|
3c0faf0021
|
[OpenFPGA Architecture] Add a new architecture with fully connected crossbar at CLB outputs
|
2020-09-16 17:27:24 -06:00 |
|
tangxifan
|
f42411c29e
|
[Regression Tests] Add test cases for routing multiplexer design with input/output buffers only
|
2020-09-14 16:03:43 -06:00 |
|
tangxifan
|
aaf63050bb
|
[OpenFPGA architecture] Add the architecture where routing multiplexers have only output buffers
|
2020-09-14 15:58:34 -06:00 |
|
tangxifan
|
aa9521b23b
|
[OpenFPGA architecture] Add the architecture where routing multiplexers have only input buffers
|
2020-09-14 15:57:44 -06:00 |
|
tangxifan
|
eecfd186f0
|
[OpenFPGA Architecture] Add the openfpga architecture for multiplexers without buffers
|
2020-09-14 15:46:10 -06:00 |
|
tangxifan
|
9bf0e772a3
|
[Regression Tests]Add a new testcase for routing multiplexer designs without buffers
|
2020-09-14 15:45:35 -06:00 |
|
tangxifan
|
4b3142c4ee
|
[Architecture File] Patch openfpga architecture with default circuit model definition
|
2020-08-23 15:13:28 -06:00 |
|
tangxifan
|
9101ba1021
|
[Architecture Language] Update openfpga architecture files for default models
|
2020-08-23 14:55:44 -06:00 |
|
tangxifan
|
6c925dcded
|
[regression test] Add more tests for thru channels and deploy to CI
|
2020-08-19 20:11:37 -06:00 |
|
tangxifan
|
881672d46a
|
update thru channel arch for avoid buggy pin locations
|
2020-08-19 19:52:35 -06:00 |
|
tangxifan
|
bf08e1841c
|
add new test case using thru channels
|
2020-08-19 17:58:34 -06:00 |
|
tangxifan
|
f0bc6f83f1
|
disable buffer absorbing in the template script for bitstream generation. This is applicable to a wide range of benchmarks
|
2020-08-19 15:34:59 -06:00 |
|
tangxifan
|
18735894f9
|
bug fix in openfpga arch: data1 and out1 should have the same offset as the data2 and out2
|
2020-08-19 15:27:30 -06:00 |
|
tangxifan
|
3273f441fe
|
bug fix in the flagship vpr arch
|
2020-08-19 15:23:20 -06:00 |
|
tangxifan
|
aa4a9b28cc
|
start testing the initial offset in the flagship architecture
|
2020-08-19 15:03:46 -06:00 |
|
tangxifan
|
f64079641d
|
bug fix in flagship vpr arch with frac mem and dsp
|
2020-08-19 12:43:58 -06:00 |
|
tangxifan
|
d7efdf35b6
|
add custom pin location to the flagship vpr arch with frac mem and dsp
|
2020-08-19 11:15:25 -06:00 |
|
tangxifan
|
dbd93e429d
|
now pro_blif.pl can accept customized clock name
|
2020-08-19 09:43:44 -06:00 |
|
tangxifan
|
743167521a
|
add Verilog design for fracturable 32k memory
|
2020-08-18 21:13:46 -06:00 |
|
tangxifan
|
42b5ea2cb1
|
bug fix in openfpga arch for frac mem and dsp
|
2020-08-18 20:42:36 -06:00 |
|
tangxifan
|
3ee4e10aa8
|
bug fix in the frac mem & DSP vpr arch
|
2020-08-18 17:25:45 -06:00 |
|
tangxifan
|
098859fe06
|
bug fix in the frac memory & DSP architecture
|
2020-08-18 15:05:51 -06:00 |
|
tangxifan
|
21c7eaa9cf
|
add 36-bit fracturable multiplier Verilog
|
2020-08-18 14:06:08 -06:00 |
|
tangxifan
|
f833e0ec66
|
add a flagship architecture using fracturable memory and dsp
|
2020-08-17 17:49:51 -06:00 |
|
tangxifan
|
1ca2829868
|
update readme for vpr architecture naming
|
2020-08-17 13:54:26 -06:00 |
|
tangxifan
|
cadf29022e
|
add README to explain the organization of regression tests
|
2020-07-28 13:44:06 -06:00 |
|
tangxifan
|
f33422d4d7
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
tangxifan
|
534c609e17
|
add fixed layouts to a flagship architecture to test bitstream generation runtime
|
2020-07-28 11:51:50 -06:00 |
|
tangxifan
|
a156807559
|
enrich basic regression tests to cover more critical microbenchmarks
|
2020-07-27 19:47:43 -06:00 |
|
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
|
tangxifan
|
31e7a753a6
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-27 19:22:16 -06:00 |
ganeshgore
|
747c062f86
|
BugFix : Flow script accepts extra OpenFPGA arguments
|
2020-07-27 18:10:43 -06:00 |
|
tangxifan
|
50cc4dfba3
|
classify regression test to dedicated categories
|
2020-07-27 17:18:59 -06:00 |
|
tangxifan
|
5595ee9052
|
refine the test case for load external arch bitstream
|
2020-07-27 16:53:29 -06:00 |
|
tangxifan
|
cec6bf0b6f
|
add or2 microbenchmark for testing external arch bitstream
|
2020-07-27 15:59:03 -06:00 |
|
tangxifan
|
4174fbf77d
|
add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
|
2020-07-27 15:54:46 -06:00 |
|
tangxifan
|
a3eba8acbe
|
update task files using the new syntax on SHELL variables
|
2020-07-27 15:25:49 -06:00 |
|
tangxifan
|
615b557dc4
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-27 14:48:23 -06:00 |
|
tangxifan
|
dc7012d590
|
update regression tests for split fabric_bitstream commands
|
2020-07-27 14:24:48 -06:00 |
|
ganeshgore
|
45af056304
|
TASK_NAME and TASK_DIR variables are avaialble in config file now
|
2020-07-27 14:14:57 -06:00 |
|
ganeshgore
|
0e46e0d857
|
Updated task.conf format to have transparent shell variables
|
2020-07-27 14:08:58 -06:00 |
|
tangxifan
|
177de90822
|
bug fix in example scripts
|
2020-07-26 22:10:04 -06:00 |
|
tangxifan
|
f687774452
|
bug fix in template scripts
|
2020-07-26 21:46:03 -06:00 |
|
tangxifan
|
41a76126b9
|
add fabric bitstream writer to CI
|
2020-07-26 21:44:42 -06:00 |
|
tangxifan
|
c87f6b75b9
|
add test case for FPGA-SPICE
|
2020-07-24 19:12:35 -06:00 |
|
tangxifan
|
020154b0cd
|
add depopulate crossbar test case
|
2020-07-24 18:06:02 -06:00 |
|
tangxifan
|
021fedbc12
|
update fabric key to synchronize with new module/instance naming
|
2020-07-24 12:55:40 -06:00 |
|
tangxifan
|
fefcd88f14
|
update openfpga architecture README for power-gating
|
2020-07-22 21:55:59 -06:00 |
|
tangxifan
|
22159531c5
|
bug fix in power gating support of FPGA-Verilog
|
2020-07-22 20:21:38 -06:00 |
|
tangxifan
|
ca867ea6fa
|
add power gate inverter test case (full testbench)
|
2020-07-22 20:09:52 -06:00 |
|
tangxifan
|
87ef7f9f99
|
add power gate example architecture
|
2020-07-22 20:06:10 -06:00 |
|
tangxifan
|
8ade40713a
|
add missing architecture for CI
|
2020-07-22 14:07:39 -06:00 |
|
tangxifan
|
1a1c3885e7
|
use k6 n10 in mux designs to speed up CI
|
2020-07-22 13:54:09 -06:00 |
|
tangxifan
|
95c1fe61e1
|
use k6 n8 in mux design to speed up CI
|
2020-07-22 13:49:03 -06:00 |
|
tangxifan
|
f754c8af06
|
use k6_n10 architecture to reduce CI runtime
|
2020-07-22 13:45:55 -06:00 |
|
tangxifan
|
92c3449999
|
bug fix in the regression test due to benchmark changes
|
2020-07-22 13:17:05 -06:00 |
|
tangxifan
|
05dccadf21
|
bug fix in the testcases using yosys_vpr flow
|
2020-07-22 12:44:19 -06:00 |
|
tangxifan
|
7d39e136a4
|
enrich micro benchmarks
|
2020-07-22 12:33:52 -06:00 |
|
tangxifan
|
1d36de817f
|
adapt generate bitstream testcase to use yosys vpr flow
|
2020-07-22 12:24:34 -06:00 |
|
tangxifan
|
b96cdbf857
|
adapt preconfig test cases to use yosys_vpr flow
|
2020-07-22 12:23:39 -06:00 |
|
tangxifan
|
d8804f4ec1
|
deploy yosys_vpr flow to basic regression tests
|
2020-07-22 12:21:59 -06:00 |
|
tangxifan
|
f4e77e3bad
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-07-22 12:09:34 -06:00 |
|
ganeshgore
|
3b6cd885f3
|
BugFix: Fixed yosys_vpr with openFPGA_Shell
|
2020-07-22 11:57:04 -06:00 |
|
tangxifan
|
eb070694b5
|
fine-tune on fast configuration for configuration chain and test case for tape-out-ish architecture
|
2020-07-15 17:52:41 -06:00 |
|
tangxifan
|
ca90f337a7
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add fast configuration chain test case
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2020-07-15 11:56:47 -06:00 |
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tangxifan
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66a50742fc
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use configuration chain in the k4k4 test case to speed up CI
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2020-07-15 11:56:11 -06:00 |
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tangxifan
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1c5bede282
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update arch file with device technology binding information
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2020-07-13 19:06:51 -06:00 |
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tangxifan
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824b56f14c
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fabric key can now accept instance name only; decoders are no longer part of the key
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2020-07-06 16:42:33 -06:00 |
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tangxifan
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1e6955aaa4
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rename arch directory to be clear for its usage
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2020-07-04 19:13:28 -06:00 |
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tangxifan
|
f9a2bb0490
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Reorganize task directory
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2020-07-04 19:06:41 -06:00 |
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tangxifan
|
4f8260a7ba
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remove obselete codes and update regression tests
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2020-07-04 17:31:34 -06:00 |
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tangxifan
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1c634e4600
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add missing task file for generate bitstream test case
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2020-07-02 17:24:51 -06:00 |
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tangxifan
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adea6fcec4
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add bitstream generation only test case to CI
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2020-07-02 16:31:22 -06:00 |
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tangxifan
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73e75bf456
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add readme for OpenFPGA architecture naming
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2020-07-01 10:27:21 -06:00 |
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tangxifan
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20cf4acda0
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add readme for architecture file naming
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2020-07-01 09:54:13 -06:00 |
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tangxifan
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b2fb5f760c
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update sample key
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2020-06-27 15:01:12 -06:00 |
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tangxifan
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d526f08782
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deploy bitstream reader in openfpga shell
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2020-06-20 18:48:19 -06:00 |
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tangxifan
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3d56cd3060
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fine tuning on the script for MCNC benchmarks
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2020-06-15 20:09:46 -06:00 |
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tangxifan
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0d81f60fd8
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add new options to openfpga task configuration files
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2020-06-12 19:48:39 -06:00 |