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OpenFPGA
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5901 Commits

Author SHA1 Message Date
tangxifan 55a7b60e49
Merge pull request #1000 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-01-15 16:03:44 -08:00
github-actions[bot] 87b256f31f Updated Patch Count 2023-01-16 00:02:19 +00:00
tangxifan 7eea4fbaf0
Merge pull request #999 from lnis-uofu/local_clk 
Example for Local Clock Support
 2023-01-15 15:26:55 -08:00
tangxifan 2c9593c1d4 [test] now use a new benchmark: discrete dffn to validate the clk gen locally feature 2023-01-15 13:09:40 -08:00
tangxifan 13aed6fff5 [test] still commment verification out 2023-01-15 12:17:59 -08:00
tangxifan ac8c0e243c [core] code format 2023-01-15 12:13:59 -08:00
tangxifan cab7e04901 [core] fixed a bug in repacker to avoid routing constrained nets 2023-01-15 12:13:12 -08:00
tangxifan 758cc7a089 [test] debugging 2023-01-15 11:44:48 -08:00
tangxifan aeb54e7404
Merge branch 'master' into local_clk 2023-01-14 23:13:06 -08:00
tangxifan 14bb76ec87 [test] remove verification steps for new test but leave a todo 2023-01-14 23:06:54 -08:00
tangxifan 2a0e512ac9 [code] format 2023-01-14 23:05:42 -08:00
tangxifan 4242c39b01 [core] fixed a bug in handling design constraints in repack 2023-01-14 23:05:04 -08:00
tangxifan 297092f1fe [arch] now use a local clock as an input of a CLB 2023-01-14 22:12:00 -08:00
tangxifan eeca302bf4
Merge pull request #998 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-01-14 20:32:42 -06:00
github-actions[bot] 6a1788f0bf Updated Patch Count 2023-01-15 00:02:19 +00:00
tangxifan 5aa85d82e6 [test] deploy the new test to basic regression tests 2023-01-13 22:07:45 -08:00
tangxifan 9222d085cd [test] now use local clock as one of the pins in a clock bus, but connected to global routing 2023-01-13 22:04:56 -08:00
tangxifan 26f71656de [test] update pin constraints 2023-01-13 21:12:18 -08:00
tangxifan 1b06916e57 Merge branch 'master' of github.com:lnis-uofu/OpenFPGA into local_clk 2023-01-13 20:46:56 -08:00
tangxifan 9e462d96e0 [arch] now use a dedicated input for locally generated clock signals 2023-01-13 20:46:04 -08:00
tangxifan ada00a3e16
Merge pull request #997 from lnis-uofu/dependabot/submodules/yosys-plugins-76b39f3 
Bump yosys-plugins from `e81b0c1` to `76b39f3`
 2023-01-13 22:13:27 -06:00
tangxifan 93107c752a [test] updating test case 2023-01-13 19:53:15 -08:00
tangxifan 1fb39f803b [doc] updated vpr arch naming rules 2023-01-13 19:52:58 -08:00
tangxifan a06ee30ca0 [arch] added a new vpr arch where clock can be generated by internal logics 2023-01-13 19:35:00 -08:00
tangxifan 1353577351 [test] added a new test to validate locally generated clocks 2023-01-13 16:45:30 -08:00
tangxifan 6400605603 [benchmark] add clock divider 2023-01-13 16:39:06 -08:00
dependabot[bot] dc5f38b9a3
Bump yosys-plugins from `e81b0c1` to `76b39f3` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `e81b0c1` to `76b39f3`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](e81b0c14d5...76b39f33ee)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-01-13 07:03:50 +00:00
tangxifan c7db77e6ea
Merge pull request #996 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-01-12 18:23:21 -08:00
github-actions[bot] fdda2921b4 Updated Patch Count 2023-01-13 00:02:42 +00:00
tangxifan 0dde9b4ee0
Merge pull request #995 from lnis-uofu/doc_cleanup 
[doc] remove temp files
 2023-01-12 11:52:48 -08:00
tangxifan c7ad0c1eb8 [doc] remove temp files 2023-01-12 10:52:18 -08:00
tangxifan dba59b0460
Merge pull request #993 from lnis-uofu/ext_exec 
New command ``ext_exec`` to allow system call; Automate bus group generation in openfpga shell scripts
 2023-01-11 20:14:47 -08:00
tangxifan 0375ec8501
Merge branch 'master' into ext_exec 2023-01-11 17:19:22 -08:00
tangxifan c55d54d325 [code] format 2023-01-11 17:19:04 -08:00
tangxifan 9b109edaa1 [doc] added a new command 2023-01-11 17:14:06 -08:00
tangxifan bbf83101be [test] deploy new test to ci 2023-01-11 17:11:28 -08:00
tangxifan c7dc3ce7dc [test] pass 2023-01-11 17:10:29 -08:00
tangxifan f6f153ace4 [test] debugging 2023-01-11 17:06:31 -08:00
tangxifan d5ebbeea9a [test] adding a new test to show how to automate generation of bus group files 2023-01-11 16:59:54 -08:00
tangxifan c00c43cbd4 [core] fixed a few bugs 2023-01-11 16:39:25 -08:00
tangxifan 9bbb09ef0f [core] adding a new command 'exec_external' to run system call 2023-01-11 16:31:26 -08:00
tangxifan 9424806416
Merge pull request #992 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-01-11 16:04:02 -08:00
github-actions[bot] d7e55cfebb Updated Patch Count 2023-01-12 00:02:31 +00:00
tangxifan e6b1a6cb9d
Merge pull request #989 from lnis-uofu/dependabot/submodules/yosys-plugins-e81b0c1 
Bump yosys-plugins from `ca5bb9a` to `e81b0c1`
 2023-01-11 13:20:24 -08:00
dependabot[bot] a10aff4dec
Bump yosys-plugins from `ca5bb9a` to `e81b0c1` 
Bumps [yosys-plugins](https://github.com/SymbiFlow/yosys-symbiflow-plugins) from `ca5bb9a` to `e81b0c1`.
- [Release notes](https://github.com/SymbiFlow/yosys-symbiflow-plugins/releases)
- [Commits](ca5bb9a2ba...e81b0c14d5)

---
updated-dependencies:
- dependency-name: yosys-plugins
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-01-10 07:04:42 +00:00
tangxifan 0b2241c4e4
Merge pull request #988 from lnis-uofu/patch_update 
Pulling refs/heads/master into master
 2023-01-09 16:04:50 -08:00
github-actions[bot] a5a92b4f0c Updated Patch Count 2023-01-10 00:02:33 +00:00
tangxifan 3c0ca84158
Merge pull request #987 from lnis-uofu/dependabot/submodules/vtr-verilog-to-routing-c8f5a65 
Bump vtr-verilog-to-routing from `3637125` to `c8f5a65`
 2023-01-09 12:06:17 -08:00
tangxifan 0e4d5fdd29
Merge pull request #986 from lnis-uofu/hide_cmd 
Now hidden commands are not allowed to be called through interactive mode and script model in OpenFPGA shell
 2023-01-09 11:50:03 -08:00
dependabot[bot] 1ea99d9496
Bump vtr-verilog-to-routing from `3637125` to `c8f5a65` 
Bumps [vtr-verilog-to-routing](https://github.com/verilog-to-routing/vtr-verilog-to-routing) from `3637125` to `c8f5a65`.
- [Release notes](https://github.com/verilog-to-routing/vtr-verilog-to-routing/releases)
- [Commits](36371250eb...c8f5a653bf)

---
updated-dependencies:
- dependency-name: vtr-verilog-to-routing
  dependency-type: direct:production
...

Signed-off-by: dependabot[bot] <support@github.com>
 2023-01-09 07:06:02 +00:00