tangxifan
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129caea38c
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[Architecture] Patch configurable latch Verilog HDL with resetb
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2020-09-23 18:30:48 -06:00 |
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tangxifan
|
1864b080a2
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[Architecture] Bug fix in configurable latch Verilog HDL
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2020-09-23 18:28:45 -06:00 |
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tangxifan
|
ebb866d04a
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[Architecture] Patch frame based using ccff
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2020-09-23 18:04:14 -06:00 |
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tangxifan
|
906191e931
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[Architecture] Use strict latch Verilog HDL in frame-based procotol
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2020-09-23 17:58:13 -06:00 |
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tangxifan
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645db17168
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[Architecture] Patch DFF Verilog HDL
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2020-09-23 17:52:59 -06:00 |
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tangxifan
|
092ada39f4
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[Architecture] Add Verilog HDL for DFF with write enable
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2020-09-23 17:49:30 -06:00 |
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tangxifan
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ad385c6d69
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[Regression Test] Add test case for using SRAM cell in frame-based configuration
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2020-09-23 17:39:36 -06:00 |
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tangxifan
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1a2c66f07d
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[Architecture] Add openfpga architecture where frame-based configuration procotol uses a SRAM cell
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2020-09-23 17:34:49 -06:00 |
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tangxifan
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a3c982a83f
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[Architecture] Patch the openfpga architecture using active-low configurable latch
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2020-09-23 17:27:16 -06:00 |
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tangxifan
|
f23c25e123
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[Regression Test] Add test case for configurable latch with active-low reset
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2020-09-23 17:25:17 -06:00 |
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tangxifan
|
a94c2655c2
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[Architecture] Patch Verilog HDL for configurable latch
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2020-09-23 17:21:30 -06:00 |
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tangxifan
|
893859be37
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[Architecture] Add openfpga architecture using active-low configurable latch
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2020-09-23 17:21:00 -06:00 |
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tangxifan
|
b242ab79bd
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[OpenFPGA Flow] Add Verilog HDL for configurable latch with active-low reset
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2020-09-23 17:19:02 -06:00 |
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tangxifan
|
149d5b20bd
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[Regression Test] Add test case for fixed device support
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2020-09-23 16:47:11 -06:00 |
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tangxifan
|
c92cf71891
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[Regression Test] Add a new template script for fixed device support
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2020-09-23 16:46:41 -06:00 |
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tangxifan
|
3350695806
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[Regression test] Add test case for pattern based local routing architecture
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2020-09-23 16:06:47 -06:00 |
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tangxifan
|
1aab691e9d
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[Architecture] Add openfpga architecture using pattern based local routing
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2020-09-23 16:06:16 -06:00 |
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tangxifan
|
951a47b19c
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[Architecture] Add k4 series architecture using pattern-based local routing
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2020-09-23 16:05:39 -06:00 |
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tangxifan
|
7729f671ab
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[Regression Tests] Remove deadlink
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2020-09-22 18:35:41 -06:00 |
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tangxifan
|
51c0319657
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[Regression tests] Add test case for the k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:54 -06:00 |
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tangxifan
|
70b8b02f74
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[Architecture] Add vpr architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:32:11 -06:00 |
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tangxifan
|
72749be4bd
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[Architecture] Add OpenFPGA architecture for k4n4 with fracturable 32-bit multiplier
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2020-09-22 15:31:34 -06:00 |
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tangxifan
|
61bcbaafd8
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[Architecture] Add Verilog HDL for fracturable 32-bit multiplier
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2020-09-22 15:15:19 -06:00 |
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tangxifan
|
3d1f49fb2f
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[Regression Test] Add testcase for k4n4 with multiple segments
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2020-09-22 12:47:41 -06:00 |
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tangxifan
|
13df6c1c21
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[Architecture] Add openfpga architecture for k4n4 using multiple segments
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2020-09-22 12:36:11 -06:00 |
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tangxifan
|
8a3934b749
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[Architecture Add vpr architecture for k4n4 using multiple wire segments
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2020-09-22 12:35:39 -06:00 |
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tangxifan
|
5741664580
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[Regression Test] Add test case for k4n4 bram architecture
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2020-09-22 12:23:56 -06:00 |
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tangxifan
|
ddf999b6b9
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[Architecture] Add verilog HDL for dual-port BRAM 1k
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2020-09-22 12:23:28 -06:00 |
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tangxifan
|
26fba4a94b
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[Architecture] Add openfpga architectue for k4n4 with bram blocks
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2020-09-22 12:22:59 -06:00 |
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tangxifan
|
daf776b7b1
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[Architecture] Add k4n4 architecture with bram block for basic tests
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2020-09-22 12:22:32 -06:00 |
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tangxifan
|
3bf94b8e34
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[Regression test] Remove no local routing from fpga verilog tests
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2020-09-22 11:48:19 -06:00 |
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tangxifan
|
7ed9f76b06
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[Regression test] Move k4n4 no local routing to basic test
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2020-09-22 11:47:03 -06:00 |
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tangxifan
|
2dea97afb6
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[Regression test] reduce runtime for k4n4 test in basic testing
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2020-09-22 11:45:29 -06:00 |
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tangxifan
|
ea4dd410b7
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[Regression Test] Add k4n4 fracturable lut test case to basic test
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2020-09-22 11:41:36 -06:00 |
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tangxifan
|
dad19cac9a
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[Regression test] Add k4 series architecture: fracturable adder
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2020-09-22 11:39:18 -06:00 |
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tangxifan
|
dd192a2f54
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[Architecture] Add a k4k4 openfpga architecture with carry chain for quick test
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2020-09-22 11:34:23 -06:00 |
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tangxifan
|
7a6f5a06f7
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[Architecture] Add a k4n4 architecture with carry chain to quick test
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2020-09-22 11:33:56 -06:00 |
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tangxifan
|
aa5f5fc7e0
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[Architecture] Bring back pin equivalence for no local routing architecture
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2020-09-21 22:22:39 -06:00 |
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tangxifan
|
a8a269aa82
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[Architecture] Temporary patch for the no local routing architecture
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2020-09-21 19:51:23 -06:00 |
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tangxifan
|
acf318f184
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[Regression test] Bug fix in test case fabric_chain
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2020-09-21 18:58:35 -06:00 |
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tangxifan
|
e4291eb27e
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[Regression Tests] Now use fixed device layout in test cases for best coverage
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2020-09-21 18:44:13 -06:00 |
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tangxifan
|
7a57cc9cf4
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[Architecture] A new device layout to k4n4 to test untileable architecture
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2020-09-21 18:36:50 -06:00 |
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tangxifan
|
2bbfcb5753
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[Architecture] Add a new device layout to k4n4 for testing tileable routing
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2020-09-21 18:34:31 -06:00 |
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tangxifan
|
e1c5947143
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[Architecture] Add auto layout and fixed layout to architectures
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2020-09-21 18:01:51 -06:00 |
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tangxifan
|
936a164eee
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[OpenFPGA flow] Add a new template script to use a fixed device layout
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2020-09-21 17:48:28 -06:00 |
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tangxifan
|
d7f8b3abad
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[Architecture] Add k4 N4 untilable architecture
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2020-09-21 17:44:37 -06:00 |
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tangxifan
|
a83bc3f75c
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[Regression tests] Add test cases for the fracturable LUT4 architecture and deploy it to CI
|
2020-09-21 17:38:16 -06:00 |
|
tangxifan
|
e9c0e90544
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[Architecture] Add a VPR architectue using fracturable LUT4
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2020-09-21 17:37:26 -06:00 |
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tangxifan
|
60f328a2ab
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[Architecture] Add openfpga architecture for a small k4 fracturable FPGA
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2020-09-21 17:36:57 -06:00 |
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tangxifan
|
681e80d4b6
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[Regression tests] update frac_lut test case using more representative benchmarks
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2020-09-17 10:39:22 -06:00 |