tangxifan
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7e461b09f8
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[core] add missing file
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2024-07-02 13:22:41 -07:00 |
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tangxifan
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e00312d29e
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[test] typo
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2024-07-01 20:34:37 -07:00 |
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tangxifan
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1bfcf7574c
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[test] validate region and single syntax
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2024-07-01 20:33:28 -07:00 |
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tangxifan
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28e3cb799e
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[test] update 2-clock arch and pcf
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2024-06-29 17:40:20 -07:00 |
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tangxifan
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12c9686c27
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[test] fixed some bugs on arch
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2024-06-29 17:38:34 -07:00 |
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tangxifan
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5dd0549aed
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[core] typo
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2024-06-29 17:17:54 -07:00 |
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tangxifan
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bc2f02866d
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[test] update testcase for 2-clk on programmable clock network
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2024-06-29 17:17:05 -07:00 |
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tangxifan
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286df30947
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[test] update clock arch xml syntax
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2024-06-29 11:02:17 -07:00 |
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tangxifan
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67554cb8d8
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[test] now use correct pcf for clock network testcases
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2024-06-29 10:04:03 -07:00 |
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tangxifan
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8bc37080fa
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[core] debuggging
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2024-06-28 23:06:21 -07:00 |
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tangxifan
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1c69365938
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[core] debugging
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2024-06-28 18:17:38 -07:00 |
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tangxifan
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f1a4304ee7
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[test] add new testcases for validate clock tree disable functions
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2024-06-28 13:43:53 -07:00 |
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tangxifan
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ad5795bece
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[test] add extra options to route clock rr_graph command in examples
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2024-06-28 13:39:41 -07:00 |
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tangxifan
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cab649893b
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[core] update clock architecture
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2024-06-26 18:06:39 -07:00 |
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tangxifan
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2cbb04b90d
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[test] add a new testcase to validate programmable clock network with internal drivers
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2024-06-25 11:58:05 -07:00 |
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tangxifan
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9bb076d892
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[test] fixed a bug on pin mapping of tetbenche
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2024-06-21 20:29:21 -07:00 |
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tangxifan
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8d7dba2d57
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[test] add a new testcase to programmable clock network on supporting reset signals
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2024-06-21 18:13:37 -07:00 |
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tangxifan
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6c5988575c
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[test] update clock network testcase
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2024-06-21 16:59:21 -07:00 |
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tangxifan
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fba0a83679
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[test] debugging 2-clock network
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2023-04-20 14:44:01 +08:00 |
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tangxifan
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02b02d18a5
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[test] fixed a bug in clock arch
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2023-04-20 11:35:36 +08:00 |
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tangxifan
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b242fd97d6
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[test] adding new arch and testcase for 2-clock network
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2023-04-20 11:31:49 +08:00 |
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tangxifan
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03cb664049
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[test] now clock network example script supports multiple clocks
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2023-04-20 10:56:36 +08:00 |
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tangxifan
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7d333b3669
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[test] add a new test for clock network: validate full testbench is working
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2023-04-20 10:36:08 +08:00 |
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tangxifan
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1f9c1fe7e1
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[test] clean up clock network task config
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2023-04-20 10:31:22 +08:00 |
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tangxifan
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fd1c4039d3
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[test] typo
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2023-03-02 21:37:24 -08:00 |
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tangxifan
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02b50e3464
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[lib] now clock spine requires explicit definition of track type and direction when coordinate is vague
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2023-03-02 21:33:32 -08:00 |
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tangxifan
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b9f7c72a96
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[test] fixed some bugs in arch
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2023-03-02 18:16:59 -08:00 |
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tangxifan
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780dec6b1b
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[test] add a new test to validate the programmable clock arch
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2023-02-28 21:46:57 -08:00 |