Lin
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88e12a0afa
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modified test cases & xsd file
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2024-10-09 17:21:49 +08:00 |
|
Lin
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f0a52bec18
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auto generate capnp no compile error
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2024-10-09 14:15:39 +08:00 |
|
Lin
|
9131e74353
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modified CMakeLists.txt
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2024-10-08 17:59:20 +08:00 |
|
Lin
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f0a9ca8b02
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add xsd file and modified cmakelist
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2024-10-08 16:30:09 +08:00 |
|
Lin
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1ba3298dbe
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add uxsdcxx
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2024-10-08 16:30:09 +08:00 |
Jingrong Lin
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be3546f7e3
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Merge branch 'master' into bin_format
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2024-10-08 13:28:53 +08:00 |
tangxifan
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b9a0b1cdf8
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[core] code format
|
2024-10-07 14:21:19 -07:00 |
|
tangxifan
|
4f96680e1f
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[core] adapt to side var changes
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2024-10-07 14:20:48 -07:00 |
|
Lin
|
ed381692a7
|
read bin format mod (with bug)
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2024-09-27 18:41:30 +08:00 |
|
Lin
|
ef18d04a3a
|
write bin function works now
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2024-09-27 17:21:24 +08:00 |
|
Lin
|
3fcdc10d3a
|
write bin function no compile error
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2024-09-27 11:34:57 +08:00 |
|
Lin
|
5174b7a336
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add capnp for unique blocks and add write bin function
|
2024-09-26 17:39:52 +08:00 |
|
Lin
|
faa222f2c1
|
create capnp folder
|
2024-09-25 18:42:04 +08:00 |
|
tangxifan
|
415fd9a8fa
|
[core] code format
|
2024-09-21 21:39:30 -07:00 |
|
tangxifan
|
9e461284d0
|
[core] standardize API for clock network intermeidate drivers
|
2024-09-21 21:38:32 -07:00 |
|
tangxifan
|
1332d426c7
|
[core] code format
|
2024-09-20 17:42:53 -07:00 |
|
tangxifan
|
965ee2190e
|
[core] support intermediate driver in clock arch
|
2024-09-20 17:42:26 -07:00 |
|
tangxifan
|
8e04d473f2
|
[core] code format
|
2024-09-18 21:10:31 -07:00 |
|
tangxifan
|
44a07704ff
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[core] add check codes for last stage pgl model
|
2024-09-18 21:10:02 -07:00 |
|
tangxifan
|
f6b645fd25
|
[core] code format
|
2024-09-18 17:44:55 -07:00 |
|
tangxifan
|
82878063c1
|
[core] syntax
|
2024-09-18 17:32:04 -07:00 |
|
tangxifan
|
47e30c3e4b
|
[core] support last stage mux
|
2024-09-18 17:26:44 -07:00 |
|
tangxifan
|
82cf7bbb8c
|
[core] Add verbose mode on find_node() for clock rr graph
|
2024-08-02 17:47:41 -07:00 |
|
tangxifan
|
ae1100ceba
|
[core] cleanup debug message
|
2024-08-02 17:05:59 -07:00 |
|
tangxifan
|
ad38b52a23
|
[lib] code format
|
2024-08-02 12:41:00 -07:00 |
|
tangxifan
|
1a13c5f815
|
[lib] now fabric key assistant can cross-check mismatches between reference and input fabric keys
|
2024-08-02 12:31:55 -07:00 |
chungshien-chai
|
766df0a1b5
|
Improve Port Parser
|
2024-07-31 12:19:30 -07:00 |
|
chungshien-chai
|
0d9f1a3c6b
|
Forward searching the config bit + some minor refactor
|
2024-07-28 19:12:34 -07:00 |
|
chungshien-chai
|
9882394c8b
|
Use archfpga_throw
|
2024-07-28 02:53:18 -07:00 |
|
chungshien-chai
|
2a3d69aded
|
Update code based on feedback
|
2024-07-28 02:37:15 -07:00 |
|
chungshien-chai
|
933155b08f
|
Update test flow
|
2024-07-27 23:52:54 -07:00 |
|
chungshien-chai
|
e60777d23e
|
Use Bitstream Setting XML
|
2024-07-26 01:36:49 -07:00 |
|
tangxifan
|
c96f899c53
|
[core] code format
|
2024-07-10 15:07:26 -07:00 |
|
tangxifan
|
a4538fb25b
|
[core] now supports to_pin in building clock network for internal driver
|
2024-07-10 15:01:18 -07:00 |
|
tangxifan
|
b2fc47a12a
|
[core] reworked i/o for clock network files
|
2024-07-10 14:34:54 -07:00 |
|
tangxifan
|
079e6f2fca
|
[core] add new syntax to support from_pin and to_pin for internal driver in clock network
|
2024-07-10 14:28:28 -07:00 |
|
tangxifan
|
0f78803759
|
[core] fixed a bug on connecting clk/rst pins from programmable network any CLB inputs
|
2024-07-09 20:47:15 -07:00 |
|
tangxifan
|
578d7c8ec0
|
[core] fixed a bug on region tap point identification
|
2024-07-01 20:58:41 -07:00 |
|
tangxifan
|
73b30841a7
|
[lib] typo
|
2024-07-01 20:56:27 -07:00 |
|
tangxifan
|
60e6e27e54
|
[core] fixed a bug on tap point identificatin
|
2024-07-01 20:45:55 -07:00 |
|
tangxifan
|
a85a6f1674
|
[core] code format
|
2024-07-01 17:57:10 -07:00 |
|
tangxifan
|
70428fd969
|
[lib] add sanity checks on global port name and clock network's global port name
|
2024-07-01 17:56:29 -07:00 |
|
tangxifan
|
df23daf026
|
[lib] sanity check on global port name and from pin name of tap points
|
2024-07-01 17:37:16 -07:00 |
|
tangxifan
|
7c487eadc9
|
[core] now clock network keep port info in a native data structure
|
2024-07-01 16:58:23 -07:00 |
|
tangxifan
|
3afb92d6a5
|
[core] code format
|
2024-06-30 22:48:15 -07:00 |
|
tangxifan
|
1fd974d544
|
[core] fixed a bug where clock network size cannot impact global port on top module
|
2024-06-29 17:35:47 -07:00 |
|
tangxifan
|
34fb003911
|
[core] replace width syntax with global port name
|
2024-06-29 10:46:00 -07:00 |
|
tangxifan
|
5cfd23747b
|
[core] code format
|
2024-06-28 13:47:03 -07:00 |
|
tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
cab649893b
|
[core] update clock architecture
|
2024-06-26 18:06:39 -07:00 |