Commit Graph

191 Commits

Author SHA1 Message Date
tangxifan ad2d101554 [test] deploy new benchmarks 2024-06-02 14:23:08 -07:00
tangxifan f25081eb31 [test] add a new test to validate ecb when tile modules are used 2024-05-20 21:10:49 -07:00
tangxifan 653521755b [test] add new testcase for ecb to basic regtest 2024-05-20 12:09:12 -07:00
tangxifan 372e386330 [test] add new tests to verify rr graph preloading in two file formats 2024-05-09 23:10:45 -07:00
tangxifan 10470b311d [test] now use latest python3 of ubuntu 22.04 2024-05-06 11:44:45 -07:00
chungshien dd577e37e0
LUTRAM Support (#1595)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric

* LUTRAM Support Phase 1

* Add Test

* Add more protocol checking to enable LUTRAM feature

* Move the config setting under config protocol

* Revert any changes

---------

Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
tangxifan d51832a4e2 [ci] typo 2024-04-11 15:13:20 -07:00
tangxifan e85df6dcfd [ci] deploy new tests to basic reg tests 2024-04-11 15:11:41 -07:00
tangxifan 4dedee4011 [test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command 2024-04-11 12:59:13 -07:00
tangxifan f0639b4567 [test] add new testcase to basic reg test 2024-03-29 11:56:11 -07:00
chungshien 4365d160ff
Support extracting data that is not affecting fabric bitstream (#1566)
* BRAM preload data - generic way to extract data from design

* Add docs and support special __layout__ case

* Add test

* Fix warning

* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
tangxifan b182b47d0b [test] use a timing-focus tool path for a testcase 2023-12-12 13:28:35 -08:00
tangxifan 6a5df804b9 [test] add new testcase to reg test 2023-12-08 13:46:54 -08:00
tangxifan d78f18d235 [test] add new testcase 2023-11-13 14:11:34 -08:00
tangxifan 8e875f3453 [test] add a new test case to validate the new feature 2023-11-02 21:08:36 -07:00
tangxifan c6f33bcd7f [test] add new tests to cover the new features 2023-10-06 18:41:57 -07:00
tangxifan 7d83fc914c [core] ad a new test case 2023-10-06 18:31:54 -07:00
tangxifan 5aa206e616 [core] fixed some bugs 2023-09-25 22:27:24 -07:00
tangxifan 60b8c396dc [test] add a new test 2023-09-25 21:25:21 -07:00
tangxifan 663c9c9fa1 [test] add a new test to validate the tile port merge feature 2023-09-25 18:34:34 -07:00
tangxifan 195aa7a9a8 [test] developing new test to increase coverage on module renaming 2023-09-23 12:40:20 -07:00
tangxifan 11e976ec92 [test] add a new test to validate renaming on fpga top/core modules 2023-09-17 17:38:37 -07:00
tangxifan 0ef1e0bde5 [test] add a new test to validate renaming rules 2023-09-17 13:29:12 -07:00
tangxifan 559fa45d89 [test] add a new test to validate module renaming using index 2023-09-16 17:55:52 -07:00
tangxifan 56cedf6c8b [test] added a new test case to validate the support on different wire segment distribution on X and Y 2023-08-22 11:20:14 -07:00
tangxifan 1b132fd667 [test] add a new testcase to validate the support on different routing channel width on X and Y 2023-08-22 11:06:12 -07:00
tangxifan 15a8d8a76a [test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation 2023-08-18 21:59:06 -07:00
tangxifan 5f6050d404 [test] add a new test to validate combo: group tile, tile annotation and subtile 2023-08-18 21:48:40 -07:00
tangxifan 5ac8919ce0 [test] add a new testcase to validate subtile with tile annotations 2023-08-18 21:37:15 -07:00
tangxifan e82e4f487e [test] add a new test to validate io subtile support 2023-08-18 11:13:34 -07:00
tangxifan 913c232556 [test] deploy new test to basic reg test 2023-08-17 14:54:24 -07:00
tangxifan 16f102f4c1 [test] deploy new tests to basic regression tests 2023-08-11 13:07:41 -07:00
tangxifan b7048d3dc8 [test] adding new tests to validate group config block 2023-08-03 22:30:41 -07:00
tangxifan 3d56bd0ff2 [test] deploy the new test to ci 2023-07-27 17:03:55 -07:00
tangxifan 46e58a56cb [test] added a new test case to validate clock network when using the tile modules 2023-07-27 16:39:48 -07:00
tangxifan e9f2adf3f9 [test] add a new testcase to validate carry chain connections when using tile modules 2023-07-27 16:06:43 -07:00
tangxifan 1ea8a33d4b [test] add a new testcase to validate global tile connections on tile modules 2023-07-27 15:57:38 -07:00
tangxifan a2848940df [test] add a new testcase to ease debugging 2023-07-26 22:32:03 -07:00
tangxifan 5685fbd5e8 [test] adding a new test case to validate the tile modules on 4x4 fabric 2023-07-26 22:17:39 -07:00
tangxifan 0db4ef62e8 [test] add a new test for tile-based fabric: using preconfig testbenches 2023-07-25 15:48:14 -07:00
tangxifan 82fe63297a [test] add a new test for top-left tile grouping 2023-07-19 11:22:36 -07:00
tangxifan 930d98f2af [test] deploy new tests 2023-07-08 21:52:16 -07:00
tangxifan 919d6d8608 [test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches 2023-06-25 22:49:51 -07:00
tangxifan 962ba67e36 [test] adding new tests to validate fpga core wrapper naming rules 2023-06-23 14:47:21 -07:00
tangxifan efc9bf9907 [test] added new test case to validate bitstream generation 2023-06-19 12:40:37 -07:00
tangxifan 97b089ae3c [test] added new testcases to validate fpga core wrapper 2023-06-18 21:01:37 -07:00
tangxifan e1feebc96d [core] fixing bugs on pcf and bgf support for mock efpga wrapper 2023-05-26 21:54:08 -07:00
tangxifan 812553e13d [test] adding more test cases 2023-05-25 20:17:23 -07:00
tangxifan df771cb33a [test] add a new testcase for subtile and deploy it to basic regression test 2023-05-03 15:41:29 +08:00
tangxifan f06248a1b0 [test] add a new testcase to validate the ccff v2 2023-04-24 14:55:22 +08:00