91c4336a4a
[test] add a new testcase to validate 3-layer clock architecture
2024-08-02 18:18:49 -07:00
84c2b27c7b
[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
2024-08-02 17:24:44 -07:00
b3c8c529d5
Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
2024-07-31 12:25:37 -07:00
3181f2d5a3
[test] add a new test to validate multiple entry points for a clock network
2024-07-30 14:17:14 -07:00
687f03fd77
[test] add a new test to validate clock network on module named by index
2024-07-30 14:06:53 -07:00
ad275fba44
[test] add a new test to validate clock network entry point on a y-direction cb
2024-07-30 12:48:35 -07:00
933155b08f
Update test flow
2024-07-27 23:52:54 -07:00
9641aaf6c4
Update test
2024-07-26 02:17:25 -07:00
2ef362d53d
Init support overwriting bitstream
2024-07-25 17:40:46 -07:00
e5d146a67a
[test] add new tests to validate rst on lut and clk on lut features
2024-07-09 20:24:23 -07:00
41839bfd7a
[test] typo
2024-07-08 20:21:40 -07:00
6492d43a01
[test] add a new test to validate perimeter cb using global tile clock
2024-07-08 11:29:20 -07:00
1a5e2392fc
[test] add a new testcase to validate clock network when perimeter cb is on
2024-07-07 22:32:13 -07:00
a46820b7c1
[core] add a new test for bottom-left tile grouping
2024-07-05 18:00:37 -07:00
a78fddc3cb
[test] add a new testcase to validate perimeter cb
2024-07-03 19:59:24 -07:00
078fad1e74
[test] typo
2024-07-02 14:57:24 -07:00
1bfcf7574c
[test] validate region and single syntax
2024-07-01 20:33:28 -07:00
f4dd222c47
[test] deploy new testcases to basic reg tests
2024-06-28 13:45:36 -07:00
2cbb04b90d
[test] add a new testcase to validate programmable clock network with internal drivers
2024-06-25 11:58:05 -07:00
7d67b9d5b9
[test] deploy new tests to basic reg tests
2024-06-21 18:14:54 -07:00
ad2d101554
[test] deploy new benchmarks
2024-06-02 14:23:08 -07:00
f25081eb31
[test] add a new test to validate ecb when tile modules are used
2024-05-20 21:10:49 -07:00
653521755b
[test] add new testcase for ecb to basic regtest
2024-05-20 12:09:12 -07:00
372e386330
[test] add new tests to verify rr graph preloading in two file formats
2024-05-09 23:10:45 -07:00
10470b311d
[test] now use latest python3 of ubuntu 22.04
2024-05-06 11:44:45 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
d51832a4e2
[ci] typo
2024-04-11 15:13:20 -07:00
e85df6dcfd
[ci] deploy new tests to basic reg tests
2024-04-11 15:11:41 -07:00
4dedee4011
[test] add a new test case to basic reg test to validate write_fabric_pin_physical_location command
2024-04-11 12:59:13 -07:00
f0639b4567
[test] add new testcase to basic reg test
2024-03-29 11:56:11 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
b182b47d0b
[test] use a timing-focus tool path for a testcase
2023-12-12 13:28:35 -08:00
6a5df804b9
[test] add new testcase to reg test
2023-12-08 13:46:54 -08:00
d78f18d235
[test] add new testcase
2023-11-13 14:11:34 -08:00
8e875f3453
[test] add a new test case to validate the new feature
2023-11-02 21:08:36 -07:00
c6f33bcd7f
[test] add new tests to cover the new features
2023-10-06 18:41:57 -07:00
7d83fc914c
[core] ad a new test case
2023-10-06 18:31:54 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
60b8c396dc
[test] add a new test
2023-09-25 21:25:21 -07:00
663c9c9fa1
[test] add a new test to validate the tile port merge feature
2023-09-25 18:34:34 -07:00
195aa7a9a8
[test] developing new test to increase coverage on module renaming
2023-09-23 12:40:20 -07:00
11e976ec92
[test] add a new test to validate renaming on fpga top/core modules
2023-09-17 17:38:37 -07:00
0ef1e0bde5
[test] add a new test to validate renaming rules
2023-09-17 13:29:12 -07:00
559fa45d89
[test] add a new test to validate module renaming using index
2023-09-16 17:55:52 -07:00
56cedf6c8b
[test] added a new test case to validate the support on different wire segment distribution on X and Y
2023-08-22 11:20:14 -07:00
1b132fd667
[test] add a new testcase to validate the support on different routing channel width on X and Y
2023-08-22 11:06:12 -07:00
15a8d8a76a
[test] added a new test to validate combo: group_tile, group_config_block, io subtile, tile annotation
2023-08-18 21:59:06 -07:00
5f6050d404
[test] add a new test to validate combo: group tile, tile annotation and subtile
2023-08-18 21:48:40 -07:00
5ac8919ce0
[test] add a new testcase to validate subtile with tile annotations
2023-08-18 21:37:15 -07:00
e82e4f487e
[test] add a new test to validate io subtile support
2023-08-18 11:13:34 -07:00
tangxifan
chungshien
chungshien-chai