tangxifan
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c8d41b4e69
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[Tool] Change routing module port naming to include architecture port names
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2021-03-14 19:35:49 -06:00 |
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tangxifan
|
956b9aca01
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[Tool] Trim dead codes in port naming function
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2021-03-13 20:23:08 -07:00 |
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tangxifan
|
2c5634ee76
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[Tool] Change pin naming of grid modules to be related to architecture port names
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2021-03-13 20:05:18 -07:00 |
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tangxifan
|
e6091fb3ff
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[Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition
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2021-02-18 21:56:30 -07:00 |
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tangxifan
|
af4cc117fb
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[Tool] bug fix in spypad lut
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2021-02-09 22:53:18 -07:00 |
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tangxifan
|
6a0f4f354f
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[Tool] Support superLUT circuit model in core engine
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2021-02-09 20:23:05 -07:00 |
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tangxifan
|
c0da6b900a
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[Tool] Bug fix in creating multi-bit clock port connections
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2021-01-12 18:38:00 -07:00 |
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tangxifan
|
65b2fe3ab7
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[Tool] Bug fix in the global tile connection by considering all the subtiles
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2021-01-10 11:52:38 -07:00 |
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tangxifan
|
9a441fa5cc
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[Tool] Upgrade openfpga to support extended global tile port definition
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2021-01-09 18:47:12 -07:00 |
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tangxifan
|
cde26597ed
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[Tool] Bug fix in scan chain builder calling
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2021-01-04 18:45:47 -07:00 |
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tangxifan
|
804b721a19
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[Tool] Bug fix in the configuration chain connection builder
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2021-01-04 17:41:29 -07:00 |
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tangxifan
|
bfd305b5a5
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[Tool] Patch the bug in finding data output ports for CCFF
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2021-01-04 17:22:30 -07:00 |
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tangxifan
|
cc91a0aebd
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[Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder
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2021-01-04 17:14:26 -07:00 |
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tangxifan
|
cb2bd2e31c
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[Tool] Remove register ports for mini local encoders (1-bit data out)
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2020-12-06 14:21:54 -07:00 |
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tangxifan
|
6bdfcb0147
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[Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming
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2020-12-05 12:44:09 -07:00 |
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tangxifan
|
6f18688f0e
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[Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module
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2020-12-05 10:53:01 -07:00 |
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tangxifan
|
5be9e9b736
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[Tool] Adapted tools to support I/O in center grid
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2020-12-04 18:50:13 -07:00 |
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tangxifan
|
3a708cff21
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[Tool] Bug fix to enable nature fracturable LUT design
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2020-11-25 23:01:18 -07:00 |
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tangxifan
|
088198c861
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[Tool] enhance error checking in fabric key parser
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2020-11-13 10:56:00 -07:00 |
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tangxifan
|
372fb261fd
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[Tool] Extend the support on global tile port for I/O tiles
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2020-11-11 15:09:40 -07:00 |
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tangxifan
|
9cbc374b33
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[Tool] Add check codes for tile annotation
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2020-11-11 12:03:13 -07:00 |
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tangxifan
|
c61ec5a8b8
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[Tool] Bug fix for defining global ports from tiles
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2020-11-10 20:31:14 -07:00 |
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tangxifan
|
dcb50e4f19
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[Tool] Use use standard data structure to store global port information
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2020-11-10 19:07:28 -07:00 |
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tangxifan
|
cbb1545ee3
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[Tool] Add connection builder for tile global ports to top-level module
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2020-11-10 16:59:00 -07:00 |
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tangxifan
|
9b0617ffe6
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[Tool] Bug fix for mappable I/O support
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2020-11-04 20:45:51 -07:00 |
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tangxifan
|
37c10f0cb5
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[Tool] Add mappable I/O support and enhance I/O support
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2020-11-04 20:21:49 -07:00 |
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tangxifan
|
4a2874b2bc
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[Tool] Refactor the codes for walking through io blocks
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2020-11-03 13:21:50 -07:00 |
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tangxifan
|
e4d974c5c8
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[Tool] Split io location mapping builder from fabric builder
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2020-11-02 18:27:34 -07:00 |
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tangxifan
|
5bcd559851
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[Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification
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2020-10-30 17:29:04 -06:00 |
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tangxifan
|
0d77916041
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[Tool] Support multi-region frame-based configuration protocol
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2020-10-30 10:43:11 -06:00 |
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tangxifan
|
8ef6ae32fb
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[Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol
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2020-10-29 17:35:55 -06:00 |
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tangxifan
|
987eccf586
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[Tool] Bug fix in multi-region memory bank; Basic test passed
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2020-10-29 16:26:45 -06:00 |
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tangxifan
|
448e88645a
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[Tool] Support multiple memory banks in top-level module
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2020-10-29 12:42:03 -06:00 |
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tangxifan
|
bd49ea95d4
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[Tool] Add function to comput configuration bits by region
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2020-10-28 12:37:09 -06:00 |
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tangxifan
|
446f982410
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[Tool] Add warning when number of regions defined in fabric key is different than architecture
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2020-10-28 11:43:05 -06:00 |
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tangxifan
|
e179a58b15
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[OpenFPGA Tool] Bug fix for long runtime
|
2020-09-28 20:42:18 -06:00 |
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tangxifan
|
47f3c79927
|
[OpenFPGA Tool] Bug fix in module manager due to configurable regions
|
2020-09-28 19:08:19 -06:00 |
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tangxifan
|
f93d46a870
|
[OpenFPGA Tool] Add multiple configuration chain support in top module builder
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2020-09-28 19:03:19 -06:00 |
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tangxifan
|
552dddffd0
|
[OpenFPGA Tool] Support configurable regions in module manager
|
2020-09-28 18:13:07 -06:00 |
|
tangxifan
|
052b8b71c7
|
[OpenFPGA Tool] Bug fix in the XML parser for fabric regions
|
2020-09-27 20:54:58 -06:00 |
|
tangxifan
|
6bea712db0
|
[OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name
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2020-09-25 14:54:51 -06:00 |
|
tangxifan
|
9adeb550dc
|
[OpenFPGA Tool] Bug fix in fabric builder
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2020-09-23 18:28:00 -06:00 |
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tangxifan
|
f284f6f8d0
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[OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs
|
2020-09-20 12:03:10 -06:00 |
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tangxifan
|
66e5e141a1
|
improve fabric key loader to reduce runtime
|
2020-07-07 10:19:34 -06:00 |
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tangxifan
|
824b56f14c
|
fabric key can now accept instance name only; decoders are no longer part of the key
|
2020-07-06 16:42:33 -06:00 |
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tangxifan
|
83e26adf90
|
add module usage types for future FPGA-SPICE development
|
2020-07-04 22:33:54 -06:00 |
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tangxifan
|
adee87569d
|
enable fast bitstream building by creating a frame view of fabric
|
2020-07-02 16:25:36 -06:00 |
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tangxifan
|
81ecfa3197
|
add comments to clarify how to select CB ports when connecting to SBs at the top level
|
2020-07-01 14:44:40 -06:00 |
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tangxifan
|
0a3c746fb1
|
now split CB module bus ports into lower/upper parts
|
2020-07-01 14:37:13 -06:00 |
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tangxifan
|
1015880d0e
|
use easy-to-access net look up in switch block module builder
|
2020-06-30 18:15:41 -06:00 |