tangxifan
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cc10b10703
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[Test] Enable more benchmarks for testing; See problems when mapping BRAMs
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2021-03-20 22:53:37 -06:00 |
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tangxifan
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169ee53b79
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[Benchmark] Add missing modules to VTR benchmarks
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2021-03-20 22:53:17 -06:00 |
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tangxifan
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eca2a35612
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[Script] Add route chan width option to vtr openfpga script
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2021-03-20 22:00:09 -06:00 |
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tangxifan
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9a3aff274f
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[Test] Use fix routing channel width to save runtime for VTR benchmarks
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2021-03-20 21:59:44 -06:00 |
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tangxifan
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ca9a70fc88
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[Test] Comment out benchmarks have problems in synthesis
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2021-03-20 21:29:21 -06:00 |
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tangxifan
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125e94a6b3
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[Test] Add full VTR benchmark (with most commented); ready for massive testing
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2021-03-20 21:01:18 -06:00 |
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tangxifan
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2bd8ef2af9
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[Benchmark] Patch boundtop.v with missing SPRAM module
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2021-03-20 21:00:53 -06:00 |
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tangxifan
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ee3677ecc1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-20 18:16:53 -06:00 |
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tangxifan
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cb07848475
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[Script] Remove verilog and SDC generation from vtr benchmark openfpga script; Focus on bitstream generation
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2021-03-20 18:11:54 -06:00 |
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tangxifan
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f3792bc6f6
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[Test] Update VTR benchmark test case to include DSP example benchmark
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2021-03-20 18:09:19 -06:00 |
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tangxifan
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477a522885
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[HDL] Rename tech lib to be consistent with arch name changes
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2021-03-20 18:08:03 -06:00 |
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tangxifan
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911979a731
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[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
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2021-03-20 18:04:59 -06:00 |
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tangxifan
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1185f7b8bf
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[Script] Add a template yosys script to enable DSP mapping
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2021-03-20 17:05:30 -06:00 |
bbleaptrot
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a6dfba4500
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Update to try and display tutorial images
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2021-03-19 16:29:25 -06:00 |
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bbleaptrot
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e90bcdc4d5
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Update to correctly include figure syntax
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2021-03-19 16:21:45 -06:00 |
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bbleaptrot
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05ec5186a2
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Update to see if .. image:: works for images
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2021-03-19 16:18:21 -06:00 |
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bbleaptrot
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4e363660e7
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Update to correct syntax for images
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2021-03-19 16:14:51 -06:00 |
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bbleaptrot
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eea73ca2bf
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Add user_defined_templates.rst file
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2021-03-19 16:10:46 -06:00 |
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bbleaptrot
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7b23231909
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Add images for user_defined_templates.v tutorial
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2021-03-19 16:08:50 -06:00 |
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tangxifan
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ed9b567d19
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Merge branch 'master' into doc_patch
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2021-03-18 22:34:43 -06:00 |
ganeshgore
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35567fb3c3
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Merge pull request #272 from lnis-uofu/yosys_heterogeneous_block_support
Yosys heterogeneous block support
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2021-03-18 16:17:55 -06:00 |
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tangxifan
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73e37060a5
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-18 15:14:24 -06:00 |
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tangxifan
|
3c1e3ed400
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Merge branch 'master' into doc_patch
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2021-03-18 15:14:05 -06:00 |
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ganeshgore
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a8f06db62f
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Merge pull request #270 from lnis-uofu/netlist_name_patch
Name grid module pins in Verilog netlist with architecture port defintion
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2021-03-18 15:13:13 -06:00 |
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tangxifan
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3ef292bdbb
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Merge branch 'netlist_name_patch' of https://github.com/LNIS-Projects/OpenFPGA into netlist_name_patch
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2021-03-17 20:28:40 -06:00 |
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tangxifan
|
fa11410425
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[Tool] Remove exceptions on outputing verilog port with lsb=0
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2021-03-17 20:27:08 -06:00 |
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tangxifan
|
d22d935322
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[CI] Update regressiont tests run in CI script
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2021-03-17 16:08:33 -06:00 |
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tangxifan
|
6bf4880c50
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[benchmark] Add vtr benchmark
|
2021-03-17 15:24:26 -06:00 |
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tangxifan
|
7a986defba
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[CI] Deploy vtr benchmark regression test to CI
|
2021-03-17 15:15:54 -06:00 |
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tangxifan
|
f9dc7c1b54
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[HDL] Add dual-port RAM 1024x8 bit HDL decription as a primitive module of OpenFPGA cells
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2021-03-17 15:15:22 -06:00 |
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tangxifan
|
08a86e056a
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[Test] Add vtr benchmark regression test
|
2021-03-17 15:13:58 -06:00 |
|
tangxifan
|
7eeb35d21f
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[Script] Bug fix in yosys script to synthesis BRAM
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2021-03-17 15:12:04 -06:00 |
|
tangxifan
|
1976a8068f
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[Test] Add test case to run vtr benchmarks (Currently, only ch_instrinsic is included; more to be added)
|
2021-03-17 15:11:17 -06:00 |
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tangxifan
|
deee7ba366
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[Script] Add example script to run vtr benchmarks
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2021-03-17 15:10:56 -06:00 |
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tangxifan
|
910f8471dd
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[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
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2021-03-17 15:10:05 -06:00 |
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tangxifan
|
76113a80fa
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[HDL] Add an adhoc yosys technology library for a heterogeneous FPGA architecture
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2021-03-17 15:09:12 -06:00 |
|
tangxifan
|
e1f8b252b1
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Merge branch 'master' into yosys_heterogeneous_block_support
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2021-03-16 20:05:21 -06:00 |
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tangxifan
|
d12a8a03fd
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[Test] Update test case using yosys bram parameters
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2021-03-16 19:52:17 -06:00 |
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tangxifan
|
094b3e9b90
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[Script] Use parameters in template yosys script supporting BRAMs
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2021-03-16 19:51:48 -06:00 |
|
tangxifan
|
cea43c2c45
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[HDL] Add SPRAM module to generic yosys tech lib for openfpga usage
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2021-03-16 18:04:31 -06:00 |
|
tangxifan
|
73b06256d0
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[Test] Deploy the new yosys script supporting BRAM to regression tests
|
2021-03-16 16:52:59 -06:00 |
|
tangxifan
|
84778bd38d
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[Script] Add new yosys script to support architectures with BRAMs
|
2021-03-16 16:52:18 -06:00 |
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tangxifan
|
090f483a11
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[Script] Now task-run script support the use of env variables openfpga_path in yosys scripts
|
2021-03-16 16:45:57 -06:00 |
|
tangxifan
|
76837e02e6
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[Script] Rename yosys script supporting bram and restructure techlib files
|
2021-03-16 16:16:53 -06:00 |
|
tangxifan
|
19b2641839
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Merge branch 'master' into doc_patch
|
2021-03-15 11:45:32 -06:00 |
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tangxifan
|
fb7d76545e
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[Doc] Patch the schematic of LUT circuit models to be consistent with netlists
|
2021-03-15 11:40:09 -06:00 |
|
tangxifan
|
87006e1374
|
Merge branch 'master' into netlist_name_patch
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2021-03-15 10:06:24 -06:00 |
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tangxifan
|
063c58b6cb
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Merge pull request #266 from lnis-uofu/ganesh_dev
[Task/Flow] Extended Yosys support in OpenFPGA task
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2021-03-15 10:06:11 -06:00 |
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tangxifan
|
d2fbda4070
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Merge branch 'master' into netlist_name_patch
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2021-03-15 09:13:04 -06:00 |
|
tangxifan
|
b080bcf018
|
Merge branch 'master' into ganesh_dev
|
2021-03-15 09:12:50 -06:00 |