tangxifan
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ca038857d3
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add lut physical truth table to physical pb
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2020-02-25 13:34:13 -07:00 |
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tangxifan
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2d86a02358
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refactored LUT bitstream generation to use vtr logic
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2020-02-25 12:45:13 -07:00 |
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tangxifan
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2c44c70557
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bring pb interconnection bitstream generation online
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2020-02-25 00:28:06 -07:00 |
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tangxifan
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04c69d30c2
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start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
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2020-02-24 19:38:02 -07:00 |
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tangxifan
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8e9660b816
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add mapped block fast look-up as placement annotation
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2020-02-24 16:09:29 -07:00 |
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tangxifan
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712eeb1340
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bring bitstream generator for routing modules online
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2020-02-23 22:09:46 -07:00 |
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tangxifan
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86c7c24701
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add fabric bitstream generation online
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2020-02-23 20:58:17 -07:00 |
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tangxifan
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8723007f68
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Bring mux bitstream generation online
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2020-02-23 20:53:24 -07:00 |
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tangxifan
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51439ba3b4
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add bitstream writer to be integrated
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2020-02-23 20:40:18 -07:00 |
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tangxifan
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2d17395e13
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start integrating fpga_bitstream. Bring data structures online
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2020-02-22 23:04:42 -07:00 |
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tangxifan
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0a01e71ba0
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Merge branch 'refactoring' into dev
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2020-02-22 22:11:27 -07:00 |
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tangxifan
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9583731531
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add results saver for lb router
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2020-02-22 22:10:32 -07:00 |
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tangxifan
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91338994c8
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Merge branch 'refactoring' into dev
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2020-02-22 18:51:51 -07:00 |
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tangxifan
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921bf7dd7b
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use constant in device annotation
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2020-02-21 20:45:22 -07:00 |
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tangxifan
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926e429374
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add save repacking results in physical pb
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2020-02-21 20:39:49 -07:00 |
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tangxifan
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12f2888c7c
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add physical pb data structure and basic allocator
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2020-02-21 17:47:27 -07:00 |
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tangxifan
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b035b4c87f
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debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
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2020-02-21 12:16:50 -07:00 |
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tangxifan
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1b66e837ba
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bug fixing for lb router. Add physical mode to default node expanding settings
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2020-02-21 11:29:00 -07:00 |
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tangxifan
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0b0e00b5f4
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debugging the LbRouter
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2020-02-20 21:56:15 -07:00 |
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tangxifan
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4abaef14b5
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bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
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2020-02-20 20:50:59 -07:00 |
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tangxifan
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3e07d7d5e0
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finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
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2020-02-20 20:26:20 -07:00 |
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tangxifan
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fdb27c5a6b
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move lb_rr_graph construction to repack command
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2020-02-20 13:24:34 -07:00 |
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tangxifan
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d8ab5536e1
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add advanced check codes for lb_rr_graph
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2020-02-19 21:41:05 -07:00 |
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tangxifan
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ed5d83178f
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add fundamental check codes for LbRRGraph
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2020-02-19 21:07:31 -07:00 |
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tangxifan
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bc27f9dd0c
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add check codes for nets inside LbRouter
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2020-02-19 20:34:30 -07:00 |
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tangxifan
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43f15e4d6f
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add methods to LbRouter for nets to be routed and access to routing traceback
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2020-02-19 16:40:53 -07:00 |
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tangxifan
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444b994285
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flatten the t_net inside LbRouter into internal data
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2020-02-19 15:37:22 -07:00 |
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tangxifan
|
2b37fcb296
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use strong id for nets to be routed in LbRouter
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2020-02-19 15:09:25 -07:00 |
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tangxifan
|
2f1bcdd27d
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use local data to store illegal modes for pb_graph_node inside LbRouter
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2020-02-19 14:53:35 -07:00 |
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tangxifan
|
5ccb4adb08
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refactored LB router main function
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2020-02-19 11:09:24 -07:00 |
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tangxifan
|
3d5a15d41e
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refactored most functions except echo and try_route() in LbRouter
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2020-02-19 00:07:36 -07:00 |
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tangxifan
|
80fa6f8a0a
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refactored skip nets in LbRouter
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2020-02-18 22:08:51 -07:00 |
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tangxifan
|
289c869caf
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refactored expand rt_node in LbRouter
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2020-02-18 22:01:22 -07:00 |
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tangxifan
|
c7ef14fc23
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refactoring node expansion in LbRouter
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2020-02-18 21:51:03 -07:00 |
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tangxifan
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11879d43b4
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add methods one by one to LbRouter from cluster_router.cpp
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2020-02-18 19:22:36 -07:00 |
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tangxifan
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0310dafe42
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add accessors to LBRouter
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2020-02-18 18:35:00 -07:00 |
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tangxifan
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1799db810d
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compilation error fix
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2020-02-18 17:04:36 -07:00 |
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tangxifan
|
d58d14df8e
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start encapsulate the whole lb router in an object
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2020-02-18 16:50:56 -07:00 |
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tangxifan
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ed25ccc70f
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start refactoring lb router in openfpga namespace
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2020-02-18 12:00:27 -07:00 |
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tangxifan
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ef11482a95
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fix dependency error in pack_types header file
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2020-02-18 11:36:16 -07:00 |
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tangxifan
|
098f7dddf3
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Merge branch 'refactoring' into dev
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2020-02-18 11:04:22 -07:00 |
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tangxifan
|
6060440b97
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fine tuning for the verbose output
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2020-02-17 21:14:15 -07:00 |
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tangxifan
|
409b3f6896
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add lb_rr_graph builder for the refactored version
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2020-02-17 21:11:56 -07:00 |
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tangxifan
|
8e97443410
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start working on repack
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2020-02-17 17:57:43 -07:00 |
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tangxifan
|
62e4f14e30
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add lb_rr_graph to device annotation
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2020-02-17 17:26:27 -07:00 |
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tangxifan
|
6c69b52ded
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Add missing file
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2020-02-17 17:11:29 -07:00 |
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tangxifan
|
92076c1460
|
refactored lb_rr_graph in the same principle of RRGraph object
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2020-02-17 16:59:24 -07:00 |
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tangxifan
|
95accb662b
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Merge branch 'refactoring' into dev
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2020-02-16 16:36:20 -07:00 |
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tangxifan
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60f40a9657
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use constant module manager as much as possible in Verilog writer
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2020-02-16 16:35:26 -07:00 |
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tangxifan
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11775c370b
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bring FPGA top module verilog writer online. Fabric Verilog generator done
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2020-02-16 16:18:14 -07:00 |