riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,034 Commits 70 Branches 8 Tags 105 MiB
Commit Graph

4034 Commits

Author SHA1 Message Date
tangxifan 5e912b3c51
Merge pull request #392 from lnis-uofu/gg_ci_cd_dev 
Make CI Portable
 2021-10-19 08:33:38 -07:00
Ganesh Gore de53943208 Removed dummy changes 2021-10-18 21:43:05 -06:00
Ganesh Gore ba7a676429 Updated docker yml 2021-10-18 21:42:39 -06:00
Ganesh Gore ed5942ce56 Added DOCKER_REPO variable 2021-10-18 20:00:21 -06:00
Ganesh Gore 32f234f4fc Made LNIS Repo as default 2021-10-18 12:54:31 -06:00
Ganesh Gore fdc9e318fd [CI] Addding conditional docker push 2021-10-18 12:18:35 -06:00
Ganesh Gore d37ae8a8c5 Changed docker repo to github repository 2021-10-18 11:34:59 -06:00
Ganesh Gore b47af70bb0 Merge branch 'master' into gg_ci_cd_dev 2021-10-18 11:17:57 -06:00
ganeshgore 36f847042d
Merge pull request #391 from xtofalex/xtof_fixes 
Typo fixes, detail error message in case of exception and message formatting in scripts
 2021-10-18 11:12:07 -06:00
Christophe Alexandre c42acec81e Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py 2021-10-18 10:45:35 +00:00
Christophe Alexandre c3dd704bf3 Fixing typo in run_fpga_flow.py 2021-10-18 09:13:42 +00:00
Christophe Alexandre d411967159 Fixing small typo in run_fpga_flow.py 2021-10-15 10:01:12 +00:00
Christophe Alexandre 1017a6a619 Fixing small typo in openfpga.sh 2021-10-11 13:52:31 +00:00
ganeshgore d85e55aef2
Merge pull request #385 from coolbreeze413/add-wget-to-dependencies 
add wget to list of dependencies
 2021-10-07 21:04:29 -06:00
coolbreeze413 f60f5b4ae5 add wget to list of dependencies 2021-10-08 03:22:30 +05:30
tangxifan 1603c9b404
Merge pull request #374 from foggy-slt/patch-1 
Update fpgaflow_default_tool_path.conf
 2021-09-21 19:02:29 -07:00
slt b867db815f
Update fpgaflow_default_tool_path.conf 
Update regex for VPR
 2021-09-17 14:02:26 +08:00
tangxifan 30feb78469
Merge pull request #364 from lnis-uofu/tutorials 
Tutorials
 2021-09-04 19:07:46 -07:00
tangxifan 801b91f776
Merge branch 'master' into tutorials 2021-08-31 17:17:40 -07:00
Andrew Pond 3c041b6012
Merge pull request #363 from lnis-uofu/compilation_readme 
Update compile.rst
 2021-08-17 11:08:14 -06:00
Andrew Pond 7537118843
Merge branch 'master' into compilation_readme 2021-08-17 10:19:31 -06:00
ANDREW HARRIS POND 1c09b8c3e0 fixed python instruction 2021-08-17 10:18:51 -06:00
ganeshgore d14a7f74f0
Merge pull request #366 from WRansohoff/accept_absolute_task_paths 
Accept absolute project paths in the 'run_fpga_task.py' script
 2021-08-13 11:17:33 -06:00
Will c31c1d8b04 Accept absolute project paths as inputs to the 'run_fpga_task.py' script. 2021-08-13 11:08:09 -04:00
bbleaptrot 814d290463
Merge branch 'master' into tutorials 2021-08-05 10:24:34 -06:00
bbleaptrot c867c7e628
Update index to include FAQ page 2021-07-28 10:14:31 -06:00
bbleaptrot 2bb76e4a82
Update to include suggested changes 2021-07-28 10:13:25 -06:00
bbleaptrot 17d3fb5d5e
Add FAQ to source folder to go along in appendix 2021-07-28 10:10:17 -06:00
Andrew Pond a8a8c25a21
Update compile.rst 2021-07-26 15:18:23 -06:00
Andrew Pond 1c0bec1c5a
Update compile.rst 2021-07-26 15:17:25 -06:00
Andrew Pond 3ce866f2eb
Update compile.rst 2021-07-26 15:12:59 -06:00
tangxifan 223e06d23c
Merge pull request #359 from lnis-uofu/pin_constraint_polarity 
Add Test Cases for the Signal Polarity Support in Pin Constraint Files
 2021-07-02 18:51:24 -06:00
tangxifan 9f03ecb160 [Test] Patch test case due to the changes in counter benchmarks 2021-07-02 17:57:39 -06:00
tangxifan 64dcdaec61 [Test] Update all the tasks that use counter benchmark 2021-07-02 17:29:13 -06:00
tangxifan 5a6874e9f1 [Benchmark] Rename the dual clock counter benchmark to follow the naming convention on counter benchmarks 2021-07-02 17:28:17 -06:00
tangxifan 8baf60603a [Script] Patching the run_fpga_task.py on pin constraint files 2021-07-02 15:59:29 -06:00
tangxifan e9d29e27e5 [Tool] Bug fix 2021-07-02 15:32:30 -06:00
tangxifan fdf94cba83 Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 15:28:34 -06:00
tangxifan 3cbe266c44 [Test] Bug fix on the test case for multi-mode FF and pin constraints 2021-07-02 15:27:27 -06:00
Ganesh Gore c67807868c [bugFix] Benchamrk variable declaration 2021-07-02 15:26:39 -06:00
tangxifan 6e6c3e9fa4 [Tool] Patch the critical bug in the use of signal polarity in pin constraints 2021-07-02 15:26:21 -06:00
tangxifan 3aacce2a96 Merge branch 'pin_constraint_polarity' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 14:04:42 -06:00
tangxifan a5101be2f6 Merge branch 'master' of https://github.com/LNIS-Projects/OpenFPGA into pin_constraint_polarity 2021-07-02 13:58:33 -06:00
tangxifan 2214575a0a
Merge pull request #358 from lnis-uofu/ganesh_dev 
Testcase for benchmark specific variables
 2021-07-02 13:54:07 -06:00
Ganesh Gore edd5be2cae [CI] Added testcase for benchmark variable 2021-07-02 12:51:34 -06:00
tangxifan dcb89cb16b [Arch] Patch architecture due to missing mode bit definition 2021-07-02 11:41:29 -06:00
tangxifan 5286f9ba25 [Test] Reworked the test case for k4n4 multi-mode FF architecture by including more counter benchmarking 2021-07-02 11:39:00 -06:00
ganeshgore b8bed59ecf
Merge pull request #356 from lnis-uofu/pin_constraint_polarity 
[WIP] Support custom default value in Pin Constraint File
 2021-07-02 10:20:20 -07:00
tangxifan 02fd2a69b3 [Script] Add dff with active-low async reset to default yosys tech lib 2021-07-02 11:17:43 -06:00
tangxifan 477e535344 [HDL] Added a multi-mode FF design with configurable asynchronous reset 2021-07-02 11:13:03 -06:00