tangxifan
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d9d57aad42
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[Tool] Added default net type options to verilog testbench generator command
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2021-06-14 11:37:49 -06:00 |
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tangxifan
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7ade48343c
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[Tool] Deprecate command 'write_verilog_testbench'
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2021-06-09 17:06:01 -06:00 |
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tangxifan
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2299ce3157
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[Tool] Preconfigured testbench writer now supports icarus simulator
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2021-06-09 13:49:25 -06:00 |
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tangxifan
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3bc8e760db
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[Tool] Add '--fabric_netlist' option to 'write_preconfigured_testbench' command
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2021-06-09 11:14:45 -06:00 |
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tangxifan
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89fb672631
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[Tool] Fine-tune the options of 'write_simulation_task_info' to be straightforward to use
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2021-06-09 10:49:00 -06:00 |
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tangxifan
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97396eda2b
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[Tool] Add a new command 'write_simulation_task_info'
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2021-06-08 22:10:02 -06:00 |
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tangxifan
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d2275b971d
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[Tool] Add a new command 'write_preconfigured_testbench'
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2021-06-08 21:53:51 -06:00 |
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tangxifan
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8db19c7af9
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[Tool] Add a new command 'write_preconfigured_fabric_wrapper'
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2021-06-08 21:28:16 -06:00 |
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tangxifan
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81048d3698
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[Tool] Add option '--fast_configuration' to 'write_full_testbench' command
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2021-06-04 11:26:39 -06:00 |
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tangxifan
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ae6a46cd60
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[Tool] Add a new command write_full_testbench which outputs self-testable full testbench which loads external bitstream file; Currently only support configuration chain without fast configuration technique
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2021-06-03 15:41:11 -06:00 |
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tangxifan
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15e26a5602
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[Tool] Support default_net_type Verilog syntex in fabric generator
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2021-02-28 11:57:40 -07:00 |
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tangxifan
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0670c2de59
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[Tool] Deploy pin constraints to preconfig Verilog module generation
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2021-01-19 16:56:30 -07:00 |
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tangxifan
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57a24570f5
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[Tool] Move icarus and signal initialization options to testbench generator
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2020-11-22 16:01:31 -07:00 |
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tangxifan
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1ef0898f41
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[Tool] Now users can specify a different fabric netlist when generating Verilog testbench
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2020-10-12 12:31:51 -06:00 |
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tangxifan
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8b3e79766c
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add fast configuration option to fpga_verilog to speed up full testbench simulation
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2020-06-11 19:31:12 -06:00 |
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tangxifan
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bba476fef4
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add explicit port mapping support to Verilog testbench generator
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2020-06-11 19:31:07 -06:00 |
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tangxifan
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a17c14c363
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clean-up command addition and add fabric bitstream building to sample script
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2020-03-02 10:39:19 -07:00 |
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tangxifan
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078f72320f
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debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
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2020-02-27 13:24:26 -07:00 |
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tangxifan
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f558405887
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ported verilog testbench generator online. Split from fabric generator. Testing to be done
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2020-02-27 12:33:09 -07:00 |
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tangxifan
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c6c3ef71f3
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adapt all the Verilog submodule writers and bring it onlien
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2020-02-16 13:35:18 -07:00 |
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tangxifan
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8b0df8632c
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bring fpga verilog create directory online
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2020-02-15 20:38:45 -07:00 |