a1a5f8cfb6
[test] add new test to valid force clock tap mux routing
2024-11-26 17:36:02 -08:00
d71e7f7412
[test] add new test to validate default mode bit overwrite
2024-11-25 16:06:40 -08:00
3c219967df
add testcase
2024-11-01 12:15:08 +08:00
fc5c0f6965
modified testcases
2024-10-09 17:41:01 +08:00
87ca9f3006
add three testcases to test bin read and write
2024-09-29 11:09:01 +08:00
ed33b62a60
[test] add new tests to validate intermediate drivers in clock
2024-09-20 19:27:40 -07:00
7b4f06ed7d
[test] validate mux2 at last stage
2024-09-18 17:40:13 -07:00
77b188060b
Merge branch 'master' into preloading_clean
2024-09-11 11:08:49 +08:00
04a60ca4b5
Merge branch 'master' into victor_OpenFPGA_dbg
2024-09-10 11:01:47 +08:00
f912af513b
[test] add a new testcase to validate mapping gnet to msb during pb_pin_fix
2024-09-09 13:54:20 -07:00
d15025d9d2
add a task case to ease the use of compress_routing option
2024-09-09 14:18:47 +08:00
83fc1210b5
add test case of report_reference to basic_reg_test.sh
2024-09-06 18:28:23 +08:00
acce64058c
add test case
2024-08-30 14:17:42 +08:00
5153cee4dd
mod reg_test script
2024-08-26 02:47:13 -07:00
701a7a5c52
add test case
2024-08-26 02:45:57 -07:00
88fa9f8d39
add test case
2024-08-25 23:41:19 -07:00
05ef972911
[test] typo
2024-08-15 15:36:08 -07:00
2c35840457
[test] add a new test to validate CHANY clock spin in DEC
2024-08-15 14:24:31 -07:00
586dd1a510
[test] add a new and strong test to validate the disable unused clock spines
2024-08-15 10:24:58 -07:00
84cc7090ce
[test] add a new test to validate that pb pin fixup impacts global net now
2024-08-14 10:37:46 -07:00
38f1bdba4e
[test] add a new test case
2024-08-09 17:04:10 -07:00
1026df4890
[test] add new tests to validate the options for undriven inputs in verilog netlists
2024-08-06 20:58:00 -07:00
91c4336a4a
[test] add a new testcase to validate 3-layer clock architecture
2024-08-02 18:18:49 -07:00
84c2b27c7b
[test] add a new test to validate that pb_pin fix is now compatible with perimeter cb
2024-08-02 17:24:44 -07:00
b3c8c529d5
Merge branch 'lnis-uofu:master' into openfpga-overwrite-bits
2024-07-31 12:25:37 -07:00
3181f2d5a3
[test] add a new test to validate multiple entry points for a clock network
2024-07-30 14:17:14 -07:00
687f03fd77
[test] add a new test to validate clock network on module named by index
2024-07-30 14:06:53 -07:00
ad275fba44
[test] add a new test to validate clock network entry point on a y-direction cb
2024-07-30 12:48:35 -07:00
933155b08f
Update test flow
2024-07-27 23:52:54 -07:00
9641aaf6c4
Update test
2024-07-26 02:17:25 -07:00
2ef362d53d
Init support overwriting bitstream
2024-07-25 17:40:46 -07:00
e5d146a67a
[test] add new tests to validate rst on lut and clk on lut features
2024-07-09 20:24:23 -07:00
41839bfd7a
[test] typo
2024-07-08 20:21:40 -07:00
6492d43a01
[test] add a new test to validate perimeter cb using global tile clock
2024-07-08 11:29:20 -07:00
1a5e2392fc
[test] add a new testcase to validate clock network when perimeter cb is on
2024-07-07 22:32:13 -07:00
a46820b7c1
[core] add a new test for bottom-left tile grouping
2024-07-05 18:00:37 -07:00
a78fddc3cb
[test] add a new testcase to validate perimeter cb
2024-07-03 19:59:24 -07:00
078fad1e74
[test] typo
2024-07-02 14:57:24 -07:00
1bfcf7574c
[test] validate region and single syntax
2024-07-01 20:33:28 -07:00
f4dd222c47
[test] deploy new testcases to basic reg tests
2024-06-28 13:45:36 -07:00
2cbb04b90d
[test] add a new testcase to validate programmable clock network with internal drivers
2024-06-25 11:58:05 -07:00
7d67b9d5b9
[test] deploy new tests to basic reg tests
2024-06-21 18:14:54 -07:00
ad2d101554
[test] deploy new benchmarks
2024-06-02 14:23:08 -07:00
f25081eb31
[test] add a new test to validate ecb when tile modules are used
2024-05-20 21:10:49 -07:00
653521755b
[test] add new testcase for ecb to basic regtest
2024-05-20 12:09:12 -07:00
372e386330
[test] add new tests to verify rr graph preloading in two file formats
2024-05-09 23:10:45 -07:00
10470b311d
[test] now use latest python3 of ubuntu 22.04
2024-05-06 11:44:45 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
d51832a4e2
[ci] typo
2024-04-11 15:13:20 -07:00
e85df6dcfd
[ci] deploy new tests to basic reg tests
2024-04-11 15:11:41 -07:00
tangxifan
Lin
Jingrong Lin
victorzh001
Victor
chungshien
chungshien-chai