tangxifan
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8578c1ecac
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[Flow] Rename the design contraint file syntax
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2021-01-16 15:35:13 -07:00 |
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tangxifan
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9154cfdeec
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[Flow] Add comments for the design constraint file
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2021-01-16 15:34:01 -07:00 |
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tangxifan
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6ab0f71896
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[Test] Add an example of repack pin constraints file
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2021-01-16 14:38:39 -07:00 |
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tangxifan
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3b5394b45f
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[Test] Now use dedicated simulation settings for the 4-clock architecture
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2021-01-14 15:40:16 -07:00 |
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tangxifan
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314e458632
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[Test] Update task configuration to use post-yosys .v file in verification
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2021-01-13 15:42:45 -07:00 |
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tangxifan
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91f12071d5
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[Test] Use counter4bit in the multi-clock test
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2021-01-13 13:34:59 -07:00 |
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tangxifan
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250adb01cf
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[Test] Update test case to use blif_vpr flow with detailed explaination on the choice
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2021-01-13 13:18:31 -07:00 |
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tangxifan
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99e2a068fb
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[Test] Add a test case for multi-clock
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2021-01-12 18:06:25 -07:00 |
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tangxifan
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43418cd76b
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[Test] Deploy pipeplined and2 to test cases
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2021-01-10 10:28:22 -07:00 |
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tangxifan
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179b0ce304
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[Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile
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2020-11-30 18:11:47 -07:00 |
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tangxifan
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27a480b5f8
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[Test] arch name fix in the test case
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2020-11-30 17:45:54 -07:00 |
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tangxifan
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a1d3b439d3
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[Test] Add a new test case to define a global reset port from a global tile port
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2020-11-30 17:19:12 -07:00 |
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tangxifan
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655da9f3d0
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[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
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2020-11-22 16:37:19 -07:00 |
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tangxifan
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845436fa71
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[Test] Add sequential benchmark for global tile clock test case
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2020-11-17 14:34:54 -07:00 |
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tangxifan
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485258a9ea
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[Test] Add test case for global clock from tiles
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2020-11-10 19:24:25 -07:00 |