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4,228 Commits 70 Branches 8 Tags 105 MiB
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4228 Commits

Author SHA1 Message Date
ganeshgore d85e55aef2
Merge pull request #385 from coolbreeze413/add-wget-to-dependencies 
add wget to list of dependencies
 2021-10-07 21:04:29 -06:00
tangxifan 92eebd9abb [Lib] Upgrade fabric key writer to support the BL/WL shift register banks 2021-10-07 17:05:35 -07:00
tangxifan eddafb42c8 [Lib] Upgrade parser for fabric key to support shift register banks 2021-10-07 15:38:42 -07:00
coolbreeze413 f60f5b4ae5 add wget to list of dependencies 2021-10-08 03:22:30 +05:30
tangxifan a15798a4e1 [Lib] Upgrade fabric key data structure to support shift register bank definitions 2021-10-07 14:42:21 -07:00
tangxifan 75bd579474
Merge pull request #25 from RapidSilicon/qlbank_sr 
Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank
 2021-10-07 13:28:36 -07:00
tangxifan 9693a269ee [FPGA-Bitstream] Now dont' care bits are truelly seen in single-chain and flatten QuickLogic memory bank 2021-10-07 11:31:16 -07:00
tangxifan a464625101
Merge pull request #24 from RapidSilicon/qlbank_sr 
Support custom shift register clock frequency through the simulation setting file
 2021-10-06 17:53:22 -07:00
tangxifan 54a8809b3c [FPGA-Verilog] Bug fix in computing clock frequency for shift register chains 2021-10-06 16:49:28 -07:00
tangxifan 8aa2647878 [Script] Bug fix in slow clock frequency in shift register chain contraints 2021-10-06 16:49:01 -07:00
tangxifan 40b589dc6d [Doc] Update documentation about the clock definition for programming clocks in simulation settings 2021-10-06 13:50:33 -07:00
tangxifan 27153bbc89 [FPGA-Verilog] Bug fix in matching shift register clocks between verilog ports and simulation setting definition 2021-10-06 13:38:51 -07:00
tangxifan dc5aedc393 [Script] Correct naming for clocks in shifter register chain defined in simulation setting files 2021-10-06 13:36:35 -07:00
tangxifan a1eaacf5a8 [Test] Reduce the number of benchmarks in the test for fixed shift register clock frequency 2021-10-06 12:12:15 -07:00
tangxifan 554018449e [Test] Update regression test script 2021-10-06 12:10:37 -07:00
tangxifan b98a8ec718 [Test] Added the dedicated test case for fixed shift register clock frequency 2021-10-06 12:09:26 -07:00
tangxifan 169bb5fa45 [Script] Add an example simulation setting file with a fixed clock frequency for shift registers 2021-10-06 11:58:50 -07:00
tangxifan bf473f50f8 [FPGA-Verilog] Correct bugs in logging clock frequencies 2021-10-06 11:55:57 -07:00
tangxifan fcb5470baa [Lib] Add validator to check if a clock is constrained in simulation settings 2021-10-06 11:48:23 -07:00
tangxifan 82ed6b177b [FPGA-Verilog] Now consider clock constraints for BL/WL shift registers 2021-10-06 11:39:28 -07:00
tangxifan 95b877924a
Merge pull request #23 from RapidSilicon/qlbank_sr 
QuickLogic Memory Bank Now Supports Don't Care Bits in Bitstream file
 2021-10-05 20:45:57 -07:00
tangxifan 03bcf6dee5 [Doc] Update documenation for the new option ``--keep_dont_care_bits`` 2021-10-05 19:23:42 -07:00
tangxifan 189ade6c1e [Test] Bug fix 2021-10-05 19:17:34 -07:00
tangxifan f74ea5d39a [Test] Use the new openfpga shell script in don't care bit tests 2021-10-05 19:14:44 -07:00
tangxifan 4add9781d5 [Script] Add a new openfpga shell script for don't care bits outputting 2021-10-05 19:13:50 -07:00
tangxifan 50604e4589 [Test] move test cases 2021-10-05 19:02:43 -07:00
tangxifan 064ac478f3 [Test] Deploy news test to fpga-bitstream regression tests 2021-10-05 19:01:03 -07:00
tangxifan fed6c133b1 [Test] Add new tests to validate the correctness of bitstream files with don't care bits 2021-10-05 18:59:33 -07:00
tangxifan 2ea9826b17 [FPGA-Bitstream] Bug fix in wrong option name 2021-10-05 18:58:47 -07:00
tangxifan ad54c8547e [FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files 2021-10-05 18:54:02 -07:00
tangxifan fdd75c4ec8 [FPGA-Bitstream] Enable don't care bit to be outputted in bitstream file for QuickLogic memory banks 2021-10-05 17:54:07 -07:00
tangxifan 7cfffa365a
Merge pull request #22 from RapidSilicon/qlbank_sr 
QuickLogic Memory Bank Now Supports Multiple Configuration Regions
 2021-10-05 15:06:17 -07:00
tangxifan 3d062872de [Lib] Upgrade openfpga arch parser to error out for unsupported configuration protocol settings 2021-10-05 14:08:01 -07:00
tangxifan ff339312f6 [Doc] Update documentation about the limitations of multi-region configuration protocols 2021-10-05 11:55:10 -07:00
tangxifan 80fd1efd61 [Test] Add an example test key for multi-region QuickLogic memory bank using shift registers 2021-10-05 11:46:58 -07:00
tangxifan b21f212031 [Test] Replace the multi-region test with the fabric key test because the mutli region of shift-register bank is sensitive to the correctness of fabric key 2021-10-05 11:39:53 -07:00
tangxifan 492db50efe [Test] Deploy the new test to basic regression tests 2021-10-05 10:59:26 -07:00
tangxifan 52569f808e [Test] Added a test case for QuickLogic memory bank using shift registers in multiple region 2021-10-05 10:57:33 -07:00
tangxifan d2859ca1c8 [Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers 2021-10-05 10:56:20 -07:00
tangxifan 96c1994171
Merge pull request #21 from RapidSilicon/qlbank_sr 
Now QuickLogic Memory Bank Supports WLR signal in shift register-based protocols
 2021-10-04 18:17:17 -07:00
tangxifan 3efd6840a8 [Engine] Bug fix for missing WLR ports in auto-generated shift register banks 2021-10-04 16:58:01 -07:00
tangxifan fbef22b494 [Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers 2021-10-04 16:39:53 -07:00
tangxifan 13c31cb89c [Test] Deploy the qlbanksr_wlr to basic regression tests 2021-10-04 16:37:49 -07:00
tangxifan fa1908511d [Test] Added a new test case to validate QuickLogic memory using shift registers with WLR control 2021-10-04 16:36:20 -07:00
tangxifan 9a7e0f761a [Doc] Add fabric bitstream file format for QL memory bank 2021-10-04 12:29:49 -07:00
tangxifan a01fa7c282 [Doc] Add figures and text to explain the difference between the XML syntax for QuickLogic memory bank 2021-10-04 12:09:42 -07:00
tangxifan 2903f28d24
Merge pull request #20 from RapidSilicon/qlbank_sr 
Support Shift-registers-based QuickLogic's Memory Bank
 2021-10-03 17:23:07 -07:00
tangxifan 7f75c2b619 [Test] Deploy shift register -based QL memory bank test case to basic regression test 2021-10-03 16:06:44 -07:00
tangxifan 06b018cfe7 [FPGA-Bitstream] Reverse bitstream for shift register due to its FIFO nature 2021-10-03 16:05:33 -07:00
tangxifan 2badcb58f2 [FPGA-Verilog] Fixed a critical bug in verilog testbench generator for QL memory bank using BL/WL register which causes misalignment in shift register loading 2021-10-03 16:04:47 -07:00