Merge pull request #22 from RapidSilicon/qlbank_sr
QuickLogic Memory Bank Now Supports Multiple Configuration Regions
This commit is contained in:
tangxifan
GitHub
commit
7cfffa365a
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@ -47,7 +47,12 @@ Template
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Specify the number of configuration regions to be used across the fabrics. By default, it will be only 1 configuration region. Each configuration region contains independent configuration protocols, but the whole fabric should employ the same type of configuration protocols. For example, an FPGA fabric consists of 4 configuration regions, each of which includes a configuration chain. The more configuration chain to be used, the fast configuration runtime will be, but at the cost of more I/Os in the FPGA fabrics. The organization of each configurable region can be customized through the fabric key (see details in :ref:`fabric_key`).
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.. warning:: Currently, multiple configuration regions is not applicable to ``standalone`` configuration protocol.
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.. warning:: Currently, multiple configuration regions is not applicable to
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- ``standalone`` configuration protocol.
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- ``ql_memory_bank`` configuration protocol when BL/WL protocol ``flatten`` is selected
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.. note:: For ``ql_memory_bank`` configuration protocol when BL/WL protocol ``shift_register`` is selected, different configuration regions **cannot** share any WLs on the same row! In such case, the default fabric key may not work. Strongly recommend to craft your own fabric key based on your configuration region plannning!
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Configuration Chain Example
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@ -152,6 +152,12 @@ void read_xml_config_organization(pugi::xml_node& xml_config_orgz,
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if (xml_wl_protocol) {
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read_xml_wl_protocol(xml_wl_protocol, loc_data, config_protocol);
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}
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/* Throw an execption if the BL/WL protocols are different. We currently do not support it! */
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if (config_protocol.bl_protocol_type() != config_protocol.wl_protocol_type()) {
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archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_config_orgz),
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"Expect same type of protocol for both BL and WL! Other combinations are not supported yet\n");
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}
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}
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}
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@ -0,0 +1,39 @@
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<fabric_key>
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<region id="0">
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<key id="0" name="grid_io_bottom" value="1" alias="grid_io_bottom_1__0_" column="2" row="0"/>
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<key id="1" name="grid_io_bottom" value="0" alias="grid_io_bottom_2__0_" column="4" row="0"/>
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<key id="2" name="grid_io_right" value="1" alias="grid_io_right_3__1_" column="6" row="2"/>
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<key id="3" name="sb_0__1_" value="0" alias="sb_0__1_" column="1" row="3"/>
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<key id="4" name="sb_0__0_" value="0" alias="sb_0__0_" column="1" row="1"/>
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<key id="5" name="cby_0__1_" value="0" alias="cby_0__1_" column="1" row="2"/>
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<key id="6" name="grid_io_left" value="0" alias="grid_io_left_0__1_" column="0" row="2"/>
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<key id="7" name="sb_1__0_" value="0" alias="sb_1__0_" column="3" row="1"/>
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<key id="8" name="cbx_1__0_" value="0" alias="cbx_1__0_" column="2" row="1"/>
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<key id="9" name="cby_1__1_" value="0" alias="cby_1__1_" column="3" row="2"/>
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<key id="10" name="grid_clb" value="0" alias="grid_clb_1__1_" column="2" row="2"/>
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<key id="11" name="sb_2__0_" value="0" alias="sb_2__0_" column="5" row="1"/>
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<key id="12" name="cbx_1__0_" value="1" alias="cbx_2__0_" column="4" row="1"/>
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<key id="13" name="cby_2__1_" value="0" alias="cby_2__1_" column="5" row="2"/>
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<key id="14" name="grid_clb" value="2" alias="grid_clb_2__1_" column="4" row="2"/>
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<key id="15" name="sb_2__1_" value="0" alias="sb_2__1_" column="5" row="3"/>
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<key id="16" name="cbx_1__1_" value="1" alias="cbx_2__1_" column="4" row="3"/>
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<key id="17" name="sb_1__1_" value="0" alias="sb_1__1_" column="3" row="3"/>
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<key id="18" name="cbx_1__1_" value="0" alias="cbx_1__1_" column="2" row="3"/>
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</region>
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<region id="1">
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<key id="19" name="grid_io_right" value="0" alias="grid_io_right_3__2_" column="6" row="4"/>
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<key id="20" name="sb_2__2_" value="0" alias="sb_2__2_" column="5" row="5"/>
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<key id="21" name="cbx_1__2_" value="1" alias="cbx_2__2_" column="4" row="5"/>
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<key id="22" name="grid_io_top" value="1" alias="grid_io_top_2__3_" column="4" row="6"/>
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<key id="23" name="sb_1__2_" value="0" alias="sb_1__2_" column="3" row="5"/>
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<key id="24" name="cbx_1__2_" value="0" alias="cbx_1__2_" column="2" row="5"/>
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<key id="25" name="grid_io_top" value="0" alias="grid_io_top_1__3_" column="2" row="6"/>
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<key id="26" name="sb_0__2_" value="0" alias="sb_0__2_" column="1" row="5"/>
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<key id="27" name="cby_0__1_" value="1" alias="cby_0__2_" column="1" row="4"/>
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<key id="28" name="grid_io_left" value="1" alias="grid_io_left_0__2_" column="0" row="4"/>
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<key id="29" name="cby_2__1_" value="1" alias="cby_2__2_" column="5" row="4"/>
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<key id="30" name="grid_clb" value="3" alias="grid_clb_2__2_" column="4" row="4"/>
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<key id="31" name="cby_1__1_" value="1" alias="cby_1__2_" column="3" row="4"/>
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<key id="32" name="grid_clb" value="1" alias="grid_clb_1__2_" column="2" row="4"/>
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</region>
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</fabric_key>
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@ -0,0 +1,224 @@
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<!-- Architecture annotation for OpenFPGA framework
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This annotation supports the k6_N10_40nm.xml
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- General purpose logic block
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- K = 6, N = 10, I = 40
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- Single mode
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- Routing architecture
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- L = 4, fc_in = 0.15, fc_out = 0.1
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-->
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<openfpga_architecture>
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<technology_library>
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<device_library>
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<device_model name="logic" type="transistor">
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<lib type="industry" corner="TOP_TT" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="0.9" pn_ratio="2"/>
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<pmos name="pch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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<nmos name="nch" chan_length="40e-9" min_width="140e-9" variation="logic_transistor_var"/>
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</device_model>
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<device_model name="io" type="transistor">
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<lib type="academia" ref="M" path="${OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.pm"/>
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<design vdd="2.5" pn_ratio="3"/>
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<pmos name="pch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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<nmos name="nch_25" chan_length="270e-9" min_width="320e-9" variation="io_transistor_var"/>
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</device_model>
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</device_library>
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<variation_library>
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<variation name="logic_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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<variation name="io_transistor_var" abs_deviation="0.1" num_sigma="3"/>
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</variation_library>
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</technology_library>
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<circuit_library>
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<circuit_model type="inv_buf" name="INVTX1" prefix="INVTX1" is_default="true">
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<design_technology type="cmos" topology="inverter" size="1"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="buf4" prefix="buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="2" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="inv_buf" name="tap_buf4" prefix="tap_buf4" is_default="false">
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<design_technology type="cmos" topology="buffer" size="1" num_level="3" f_per_stage="4"/>
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<device_technology device_model_name="logic"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in" out_port="out">
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10e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="pass_gate" name="TGATE" prefix="TGATE" is_default="true">
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<design_technology type="cmos" topology="transmission_gate" nmos_size="1" pmos_size="2"/>
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<device_technology device_model_name="logic"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="input" prefix="sel" size="1"/>
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<port type="input" prefix="selb" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<delay_matrix type="rise" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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<delay_matrix type="fall" in_port="in sel selb" out_port="out">
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10e-12 5e-12 5e-12
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</delay_matrix>
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</circuit_model>
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<circuit_model type="chan_wire" name="chan_segment" prefix="track_seg" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="101" C="22.5e-15" num_level="1"/> <!-- model_type could be T, res_val and cap_val DON'T CARE -->
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</circuit_model>
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<circuit_model type="wire" name="direct_interc" prefix="direct_interc" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="false"/>
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<output_buffer exist="false"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<wire_param model_type="pi" R="0" C="0" num_level="1"/> <!-- model_type could be T, res_val cap_val should be defined -->
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</circuit_model>
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<circuit_model type="mux" name="mux_2level" prefix="mux_2level" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_2level_tapbuf" prefix="mux_2level_tapbuf" dump_structural_verilog="true">
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<design_technology type="cmos" structure="multi_level" num_level="2" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<circuit_model type="mux" name="mux_1level_tapbuf" prefix="mux_1level_tapbuf" is_default="true" dump_structural_verilog="true">
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<design_technology type="cmos" structure="one_level" add_const_input="true" const_input_val="1"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="tap_buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="1"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="1"/>
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</circuit_model>
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<!--DFF subckt ports should be defined as <D> <Q> <CLK> <RESET> <SET> -->
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<circuit_model type="ff" name="DFFSRQ" prefix="DFFSRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="D" lib_name="D" size="1"/>
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<port type="input" prefix="set" lib_name="SET" size="1" is_global="true" default_val="0" is_set="true"/>
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<port type="input" prefix="reset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true"/>
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<port type="output" prefix="Q" lib_name="Q" size="1"/>
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<port type="clock" prefix="clk" lib_name="CK" size="1" is_global="true" default_val="0" />
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</circuit_model>
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<circuit_model type="lut" name="lut4" prefix="lut4" dump_structural_verilog="true">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<lut_input_inverter exist="true" circuit_model_name="INVTX1"/>
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<lut_input_buffer exist="true" circuit_model_name="buf4"/>
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<pass_gate_logic circuit_model_name="TGATE"/>
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<port type="input" prefix="in" size="4"/>
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<port type="output" prefix="out" size="1"/>
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<port type="sram" prefix="sram" size="16"/>
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</circuit_model>
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<!--Scan-chain DFF subckt ports should be defined as <D> <Q> <Qb> <CLK> <RESET> <SET> -->
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<circuit_model type="sram" name="SRAM" prefix="SRAM" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/sram.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/sram.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="bl" prefix="bl" lib_name="D" size="1"/>
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<port type="wl" prefix="wl" lib_name="WE" size="1"/>
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<port type="output" prefix="out" lib_name="Q" size="1"/>
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<port type="output" prefix="outb" lib_name="QN" size="1"/>
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</circuit_model>
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<circuit_model type="iopad" name="GPIO" prefix="GPIO" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/gpio.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/gpio.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="inout" prefix="PAD" size="1" is_global="true" is_io="true" is_data_io="true"/>
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<port type="sram" prefix="DIR" size="1" mode_select="true" circuit_model_name="SRAM" default_val="1"/>
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<port type="input" prefix="outpad" lib_name="A" size="1"/>
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<port type="output" prefix="inpad" lib_name="Y" size="1"/>
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</circuit_model>
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<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
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<circuit_model type="ccff" name="BL_DFFRQ" prefix="BL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v" is_default="true">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" lib_name="SIN" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="bl" prefix="BL" lib_name="BL" size="1"/>
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<port type="clock" prefix="bl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
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</circuit_model>
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<!-- The following flip-flop is used to build the shift register chains for configuring memory banks -->
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<circuit_model type="ccff" name="WL_DFFRQ" prefix="WL_DFFRQ" spice_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/spice/dff.sp" verilog_netlist="${OPENFPGA_PATH}/openfpga_flow/openfpga_cell_library/verilog/dff.v">
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<design_technology type="cmos"/>
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<input_buffer exist="true" circuit_model_name="INVTX1"/>
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<output_buffer exist="true" circuit_model_name="INVTX1"/>
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<port type="input" prefix="srReset" lib_name="RST" size="1" is_global="true" default_val="0" is_reset="true" is_prog="true"/>
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<port type="input" prefix="D" lib_name="SIN" size="1"/>
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<port type="output" prefix="Q" lib_name="SOUT" size="1"/>
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<port type="wl" prefix="wl" lib_name="WLW" size="1"/>
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<port type="clock" prefix="wl_en" lib_name="WEN" size="1" is_global="true" default_val="0" is_prog="true"/>
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<port type="clock" prefix="wl_sr_clk" lib_name="CK" size="1" is_global="true" default_val="0" is_prog="true" is_shift_register="true"/>
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</circuit_model>
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||||
</circuit_library>
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||||
<configuration_protocol>
|
||||
<organization type="ql_memory_bank" circuit_model_name="SRAM" num_regions="2">
|
||||
<bl protocol="shift_register" circuit_model_name="BL_DFFRQ"/>
|
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<wl protocol="shift_register" circuit_model_name="WL_DFFRQ"/>
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</organization>
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||||
</configuration_protocol>
|
||||
<connection_block>
|
||||
<switch name="ipin_cblock" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</connection_block>
|
||||
<switch_block>
|
||||
<switch name="0" circuit_model_name="mux_2level_tapbuf"/>
|
||||
</switch_block>
|
||||
<routing_segment>
|
||||
<segment name="L4" circuit_model_name="chan_segment"/>
|
||||
</routing_segment>
|
||||
<pb_type_annotations>
|
||||
<!-- physical pb_type binding in complex block IO -->
|
||||
<pb_type name="io" physical_mode_name="physical" idle_mode_name="inpad"/>
|
||||
<pb_type name="io[physical].iopad" circuit_model_name="GPIO" mode_bits="1"/>
|
||||
<pb_type name="io[inpad].inpad" physical_pb_type_name="io[physical].iopad" mode_bits="1"/>
|
||||
<pb_type name="io[outpad].outpad" physical_pb_type_name="io[physical].iopad" mode_bits="0"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
|
||||
<!-- physical pb_type binding in complex block CLB -->
|
||||
<!-- physical mode will be the default mode if not specified -->
|
||||
<pb_type name="clb">
|
||||
<!-- Binding interconnect to circuit models as their physical implementation, if not defined, we use the default model -->
|
||||
<interconnect name="crossbar" circuit_model_name="mux_2level"/>
|
||||
</pb_type>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.lut4" circuit_model_name="lut4"/>
|
||||
<pb_type name="clb.fle[n1_lut4].ble4.ff" circuit_model_name="DFFSRQ"/>
|
||||
<!-- End physical pb_type binding in complex block IO -->
|
||||
</pb_type_annotations>
|
||||
</openfpga_architecture>
|
||||
|
|
@ -95,6 +95,7 @@ run-task basic_tests/fabric_key/load_external_key_cc_fpga --debug --show_thread_
|
|||
run-task basic_tests/fabric_key/load_external_key_multi_region_cc_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_qlbank_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_qlbank_fpga --debug --show_thread_logs
|
||||
run-task basic_tests/fabric_key/load_external_key_multi_region_qlbanksr_fpga --debug --show_thread_logs
|
||||
|
||||
echo -e "Testing K4 series FPGA";
|
||||
echo -e "Testing K4N4 with facturable LUTs";
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# Configuration file for running experiments
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
|
||||
# Each job execute fpga_flow script on combination of architecture & benchmark
|
||||
# timeout_each_job is timeout for each job
|
||||
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
|
||||
|
||||
[GENERAL]
|
||||
run_engine=openfpga_shell
|
||||
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
|
||||
power_analysis = true
|
||||
spice_output=false
|
||||
verilog_output=true
|
||||
timeout_each_job = 20*60
|
||||
fpga_flow=vpr_blif
|
||||
|
||||
[OpenFPGA_SHELL]
|
||||
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_secure_fabric_from_key_example_script.openfpga
|
||||
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_multi_region_qlbanksr_openfpga.xml
|
||||
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_shift_register_sim_openfpga.xml
|
||||
external_fabric_key_file=${PATH:OPENFPGA_PATH}/openfpga_flow/fabric_keys/k4_N4_2x2_multi_region_qlbanksr_sample_key.xml
|
||||
openfpga_vpr_device_layout=2x2
|
||||
|
||||
[ARCHITECTURES]
|
||||
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
|
||||
|
||||
[BENCHMARKS]
|
||||
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif
|
||||
|
||||
[SYNTHESIS_PARAM]
|
||||
bench0_top = and2
|
||||
bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act
|
||||
bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v
|
||||
bench0_chan_width = 300
|
||||
|
||||
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
|
||||
end_flow_with_test=
|
||||
#vpr_fpga_verilog_formal_verification_top_netlist=
|
||||
Loading…
Reference in New Issue