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4228 Commits

Author SHA1 Message Date
tangxifan 6f80c5b929
Merge pull request #30 from RapidSilicon/update_from_upstream 
Pulling refs/heads/update_from_upstream into master
 2021-10-20 09:18:30 -07:00
nadeemyaseen-rs 6e6225a33e
corrected the syntax error 2021-10-20 20:19:35 +05:00
nadeemyaseen-rs 101e84aaa8 added auto_fetch.yml file to create automatic PR for update_from_upstream branch 2021-10-20 20:16:41 +05:00
nadeemyaseen-rs 274252438a Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-20 20:13:46 +05:00
tangxifan 5e912b3c51
Merge pull request #392 from lnis-uofu/gg_ci_cd_dev 
Make CI Portable
 2021-10-19 08:33:38 -07:00
Ganesh Gore de53943208 Removed dummy changes 2021-10-18 21:43:05 -06:00
Ganesh Gore ba7a676429 Updated docker yml 2021-10-18 21:42:39 -06:00
Ganesh Gore ed5942ce56 Added DOCKER_REPO variable 2021-10-18 20:00:21 -06:00
Ganesh Gore 32f234f4fc Made LNIS Repo as default 2021-10-18 12:54:31 -06:00
Ganesh Gore fdc9e318fd [CI] Addding conditional docker push 2021-10-18 12:18:35 -06:00
Ganesh Gore d37ae8a8c5 Changed docker repo to github repository 2021-10-18 11:34:59 -06:00
Ganesh Gore b47af70bb0 Merge branch 'master' into gg_ci_cd_dev 2021-10-18 11:17:57 -06:00
ganeshgore 36f847042d
Merge pull request #391 from xtofalex/xtof_fixes 
Typo fixes, detail error message in case of exception and message formatting in scripts
 2021-10-18 11:12:07 -06:00
Christophe Alexandre c42acec81e Fixing python string formatting: clean_up_and_exit calls in run_fpga_flow.py 2021-10-18 10:45:35 +00:00
Christophe Alexandre c3dd704bf3 Fixing typo in run_fpga_flow.py 2021-10-18 09:13:42 +00:00
Christophe Alexandre d411967159 Fixing small typo in run_fpga_flow.py 2021-10-15 10:01:12 +00:00
tangxifan 698fc43de5
Merge pull request #28 from RapidSilicon/update_from_upstream 
Update from upstream
 2021-10-14 21:09:35 -07:00
nadeemyaseen-rs 0f10cc4c81 change the path in ci_test.sh 2021-10-14 19:43:37 +05:00
nadeemyaseen-rs e0cfd46ec7 Merge remote-tracking branch 'upstream/master' into update_from_upstream 2021-10-14 19:25:31 +05:00
tangxifan c8ffc34125
Merge pull request #26 from RapidSilicon/qlbank_multibank_sr 
Now QuickLogic Memory Bank Support Multiple Shift Register Chains in each Configuration Region
 2021-10-11 11:38:31 -07:00
tangxifan b2c4e3314e [Test] Bug fix in test cases 2021-10-11 10:28:09 -07:00
tangxifan 8566e2a0cd [Test] Renaming test case to follow naming convention as other fabric key test cases 2021-10-11 09:56:23 -07:00
tangxifan 2bf203cd00 [Test] Deploy the new test to basic regression test 2021-10-11 09:54:39 -07:00
tangxifan b8b02d37d5 [Test] Added a new test case to validate the correctness of custom shift register chain through fabric key file 2021-10-11 09:53:23 -07:00
tangxifan cdcb07256b [Arch] Add an example fabric key that models a shift-register-based QuickLogic memory bank using custom chain organization 2021-10-11 09:49:22 -07:00
tangxifan 6586ea7816 [Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture 2021-10-11 09:40:02 -07:00
Christophe Alexandre 1017a6a619 Fixing small typo in openfpga.sh 2021-10-11 13:52:31 +00:00
tangxifan 982a324e0d [Test] Temporarily disable some tests; Will go back later 2021-10-10 23:30:50 -07:00
tangxifan 546350ae41 [FPGA-Verilog] Revert back to the previous precomputing strategy for shift register clocks 2021-10-10 23:19:39 -07:00
tangxifan 40fd89fdb4 [arch] Update fabric key for multi-region 2021-10-10 22:03:49 -07:00
tangxifan b9c540ec3f [Engine] Upgrade fabric key writer to support BL/WL shift register banks 2021-10-10 21:14:14 -07:00
tangxifan 202b50c0e3 [FPGA-Verilog] Fixed a weird bug which causes totally different results in fixed and auto shift register clock freq; However, this is a dirty fix. Require further study to know why 2021-10-10 20:57:23 -07:00
tangxifan 4e2df9d69c [Lib] Bug fix in unintialized memory in fabric key 2021-10-10 17:59:11 -07:00
tangxifan 57159fc121 [Doc] Update documentation for the new syntax in configuration protocol and fabric key file format 2021-10-10 17:46:45 -07:00
tangxifan de3275e9ba [FPGA-Verilog] Fixed a critical in verilog testbench which caused the last bit of bitstream skipped when loading to shift register chains 2021-10-10 16:56:07 -07:00
tangxifan 1c46a92559 [FPGA-Bitstream] Bug fix 2021-10-09 21:59:56 -07:00
tangxifan 6aa4991314 [FPGA-Verilog] Bug fix 2021-10-09 21:34:07 -07:00
tangxifan 7810f376c8 [FPGA-Bitstream] Patch code comments 2021-10-09 21:03:01 -07:00
tangxifan 8f9e564cd5 [Test] Add the new test to basic regression test 2021-10-09 20:45:23 -07:00
tangxifan 6122863548 [Test] Add a test case to validate the multi-shift-register-chain QL memory bank 2021-10-09 20:44:28 -07:00
tangxifan 82e77b42c5 [Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA 2021-10-09 20:43:55 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan aac74d9163 [Engine] Bug fix 2021-10-09 18:46:20 -07:00
tangxifan fa08f44107 [Engine] Bug fix 2021-10-09 16:58:56 -07:00
tangxifan 19a551e641 [Engine] Upgrade fabric generator to support multiple shift register banks in a configuration region 2021-10-09 16:44:04 -07:00
tangxifan 932beb480a [Engine] Add fast look-up to the shift register bank data structure 2021-10-08 22:00:01 -07:00
tangxifan e3ff40d9e0 [Engine] Add missing return value 2021-10-08 20:17:55 -07:00
tangxifan 39a69e0d88 [Engine] Upgrading fabric generator to support customizable shift register banks from fabric key and configuration protocols 2021-10-08 17:58:06 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan f7484d4323 [Engine] Update the key memory data structure to contain shift register bank general information 2021-10-08 10:42:18 -07:00