Merge pull request #28 from RapidSilicon/update_from_upstream

Update from upstream

.github/workflows/install_dependencies_build.sh

@@ -37,4 +37,5 @@ apt-get update && apt-get install -y \
     texinfo \
     time \
     valgrind \
+    wget \
     zip

.github/workflows/install_dependencies_run.sh

@@ -1,4 +1,4 @@
 apt-get install --no-install-recommends -y \
 libdatetime-perl libc6 libffi6 libgcc1 libreadline7 libstdc++6 \
 libtcl8.6 python3.8 python3-pip zlib1g libbz2-1.0 \
-iverilog git rsync make curl
+iverilog git rsync make curl wget

ci_test.sh

@@ -1,6 +1,6 @@
 #!/bin/bash
 
-export OPENFPGA_PATH=/home/komal.javed@lmlhr.com/rapidsilicon/openfpga_new
+export OPENFPGA_PATH=~/rapidsilicon/openfpga_new
 
 for dir in RTL_Benchmark/*; do
  if [ -d "$dir" ]; then

docs/source/faq.rst

@@ -0,0 +1,47 @@
+.. _faq:
+
+Frequently Asked Questions
+==========================
+
+Where is the best place to get help with OpenFPGA?
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Currently, we have an active github issues page found `here <https://github.com/lnis-uofu/OpenFPGA/issues>`_. Users can see if their 
+questions have already been answered by searching the open or closed issues, and users are recommended to post questions there first. 
+Asking questions on the github issues page allows us to answer the question for everyone who may be experiencing similar problems as 
+well.
+
+What should I do if check-in tests failed when first installing OpenFPGA?
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+First, check to make sure all dependencies for OpenFPGA and Python have been installed and are up-to-date on the desired device. To see the full
+list of depenencies, please visit 
+`our github dependencies page <https://github.com/lnis-uofu/OpenFPGA/blob/master/.github/workflows/install_dependencies_build.sh>`_. 
+This issue has been discussed `in issue 280 <https://github.com/lnis-uofu/OpenFPGA/issues/280>`_.
+
+
+How to sweep design parameters in a task run of OpenFPGA design flow?
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Testing multiple script parameters for a variable is possible by modifying the task.conf file. Doing so will create a job for 
+each combination of the variables. A solution is discussed `in issue 228 <https://github.com/lnis-uofu/OpenFPGA/issues/228>`_.
+
+
+How do I setup OpenFPGA to be used by multiple users on a single device?
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+OpenFPGA can support multiple users on a shared device using the environment variable ``OPENFPGA_ROOT``. The OpenFPGA script for 
+running tasks needs ``OPENFPGA_ROOT`` to be the path to the OpenFPGA root directory. Users can then run the script on a task in the
+current working directory. A solution is discussed `in issue 209 <https://github.com/lnis-uofu/OpenFPGA/issues/209>`_.
+
+
+How do I contribute to OpenFPGA?
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+Users of OpenFPGA that are interested in contributing must complete the following: 
+
+    - Create a branch. For external collaborators, please fork the repository first and create a branch in the fork.
+    - Creatre a pull request and fill out our pull request template. It is easy for us to acknowledge and review your pull request.	
+    - Wait or keep debugging until all the CI tests pass.	
+    - Request for a review. You may expect several rounds of review and discussion before the pull request is approved.
+

docs/source/index.rst

@@ -36,6 +36,7 @@ Welcome to OpenFPGA's documentation!
 
    contact
    reference
+   faq
 
 For more information on the VTR see vtr_doc_ or vtr_github_
 

openfpga_flow/misc/fpgaflow_default_tool_path.conf

@@ -24,8 +24,8 @@ mult_blocks = "Netlist mult_36 blocks: ([0-9]+)", str
 memory_blocks = "Netlist memory blocks: ([0-9]+)", str
 logic_delay = "Total logic delay: ([0-9.]+)", str
 total_net_delay = "total net delay: ([0-9.]+)", str
-total_routing_area = "Total routing area: ([0-9.]+)", str
-total_logic_block_area = "Total used logic block area: ([0-9]+)", str
+total_routing_area = "Total routing area: ([0-9.]+[e|E\+[0-9]+)", str
+total_logic_block_area = "Total used logic block area: ([0-9.]+[e|E\+[0-9]+)", str
 total_wire_length = "Total wirelength: ([0-9]+)", str
 packing_time = "Packing took ([0-9.]+) seconds", str
 placement_time = "Placement took ([0-9.]+) seconds", str