tangxifan
|
df23daf026
|
[lib] sanity check on global port name and from pin name of tap points
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2024-07-01 17:37:16 -07:00 |
|
tangxifan
|
7c487eadc9
|
[core] now clock network keep port info in a native data structure
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2024-07-01 16:58:23 -07:00 |
|
tangxifan
|
58a70ad581
|
Merge pull request #1733 from lnis-uofu/patch_update
Pulling refs/heads/master into master
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2024-07-01 16:44:00 -07:00 |
github-actions[bot]
|
24e2829899
|
Updated Patch Count
|
2024-07-01 23:26:27 +00:00 |
|
tangxifan
|
69792d807f
|
Merge pull request #1732 from lnis-uofu/dependabot/submodules/yosys-a739e21
Bump yosys from `07daf61` to `a739e21`
|
2024-07-01 16:26:10 -07:00 |
dependabot[bot]
|
e007094112
|
Bump yosys from `07daf61` to `a739e21`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `07daf61` to `a739e21`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](07daf61ae6...a739e21a5f)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-07-01 06:06:57 +00:00 |
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tangxifan
|
18e2b994ac
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[doc] update syntax on clock network file
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2024-06-30 22:56:31 -07:00 |
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tangxifan
|
3afb92d6a5
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[core] code format
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2024-06-30 22:48:15 -07:00 |
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tangxifan
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28e3cb799e
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[test] update 2-clock arch and pcf
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2024-06-29 17:40:20 -07:00 |
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tangxifan
|
12c9686c27
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[test] fixed some bugs on arch
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2024-06-29 17:38:34 -07:00 |
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tangxifan
|
1fd974d544
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[core] fixed a bug where clock network size cannot impact global port on top module
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2024-06-29 17:35:47 -07:00 |
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tangxifan
|
5dd0549aed
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[core] typo
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2024-06-29 17:17:54 -07:00 |
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tangxifan
|
bc2f02866d
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[test] update testcase for 2-clk on programmable clock network
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2024-06-29 17:17:05 -07:00 |
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tangxifan
|
286df30947
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[test] update clock arch xml syntax
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2024-06-29 11:02:17 -07:00 |
|
tangxifan
|
4f787a5cfc
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[core] add more debugging message
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2024-06-29 10:54:08 -07:00 |
|
tangxifan
|
5fa674be24
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[core] fixed the bug on matching global net from pcf
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2024-06-29 10:51:45 -07:00 |
|
tangxifan
|
34fb003911
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[core] replace width syntax with global port name
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2024-06-29 10:46:00 -07:00 |
|
tangxifan
|
67554cb8d8
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[test] now use correct pcf for clock network testcases
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2024-06-29 10:04:03 -07:00 |
|
tangxifan
|
8bc37080fa
|
[core] debuggging
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2024-06-28 23:06:21 -07:00 |
|
tangxifan
|
1c69365938
|
[core] debugging
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2024-06-28 18:17:38 -07:00 |
|
tangxifan
|
0de3ff3eb8
|
[core] debugging
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2024-06-28 17:16:33 -07:00 |
|
tangxifan
|
e0b9f7860b
|
[core] fixed a bug where counter for gnets are not activated
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2024-06-28 14:10:14 -07:00 |
|
tangxifan
|
5cfd23747b
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[core] code format
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2024-06-28 13:47:03 -07:00 |
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tangxifan
|
f4dd222c47
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[test] deploy new testcases to basic reg tests
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2024-06-28 13:45:36 -07:00 |
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tangxifan
|
f1a4304ee7
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[test] add new testcases for validate clock tree disable functions
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2024-06-28 13:43:53 -07:00 |
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tangxifan
|
ad5795bece
|
[test] add extra options to route clock rr_graph command in examples
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2024-06-28 13:39:41 -07:00 |
|
tangxifan
|
1094af9f73
|
[doc] add new options to route clock graph
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2024-06-28 12:38:40 -07:00 |
|
tangxifan
|
f5b6774eb0
|
[core] add code comments and fixed some bugs
|
2024-06-28 12:21:33 -07:00 |
|
tangxifan
|
53ba2f0c29
|
[core] fixed a critical bug where some switching points are missing
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2024-06-27 15:53:17 -07:00 |
|
tangxifan
|
5a7f618f29
|
[core] debugging
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2024-06-27 15:44:17 -07:00 |
|
tangxifan
|
f4f487099d
|
[core] syntax
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2024-06-27 15:07:48 -07:00 |
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tangxifan
|
4185235a69
|
[core] now clock routing is based on tree expansion. Unused part can be disconnected
|
2024-06-27 15:02:20 -07:00 |
|
tangxifan
|
e75fd57af2
|
[core] refactor codes
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2024-06-27 12:39:18 -07:00 |
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tangxifan
|
7892c2340c
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[core] add a new option 'disable_unused_trees' to route clock rr graph
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2024-06-27 12:01:54 -07:00 |
|
tangxifan
|
3fb891094b
|
[doc] add new syntax
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2024-06-27 11:02:37 -07:00 |
|
tangxifan
|
6fceb81110
|
[core] code format
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2024-06-27 10:19:40 -07:00 |
|
tangxifan
|
64a7a4ce26
|
[core] syntax
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2024-06-27 10:19:14 -07:00 |
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tangxifan
|
9ce552495a
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[core] now internal drivers can be routed in dedicated clock network
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2024-06-27 10:17:08 -07:00 |
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tangxifan
|
53c155c02b
|
Merge pull request #1731 from lnis-uofu/patch_update
Pulling refs/heads/master into master
|
2024-06-27 09:52:57 -07:00 |
|
github-actions[bot]
|
1f4fda25eb
|
Updated Patch Count
|
2024-06-27 16:44:38 +00:00 |
|
tangxifan
|
39e0c1b635
|
Merge pull request #1730 from lnis-uofu/dependabot/submodules/yosys-07daf61
Bump yosys from `1288166` to `07daf61`
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2024-06-27 09:44:16 -07:00 |
|
dependabot[bot]
|
ec85bfc704
|
Bump yosys from `1288166` to `07daf61`
Bumps [yosys](https://github.com/YosysHQ/yosys) from `1288166` to `07daf61`.
- [Release notes](https://github.com/YosysHQ/yosys/releases)
- [Commits](1288166f7a...07daf61ae6)
---
updated-dependencies:
- dependency-name: yosys
dependency-type: direct:production
...
Signed-off-by: dependabot[bot] <support@github.com>
|
2024-06-27 06:41:45 +00:00 |
|
tangxifan
|
ac1ad52795
|
[core] code format
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2024-06-26 22:47:29 -07:00 |
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tangxifan
|
5d0b0b9a8c
|
[core] now global nets mapping are applied to clock routing
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2024-06-26 22:46:12 -07:00 |
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tangxifan
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d5d9531eec
|
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
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2024-06-26 21:52:45 -07:00 |
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tangxifan
|
cab649893b
|
[core] update clock architecture
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2024-06-26 18:06:39 -07:00 |
|
tangxifan
|
59be95b227
|
[core] code format
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2024-06-26 17:58:26 -07:00 |
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tangxifan
|
59404e5487
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[core] add verbose output
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2024-06-26 17:55:23 -07:00 |
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tangxifan
|
576a861b8d
|
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
|
2024-06-26 17:54:31 -07:00 |
|
tangxifan
|
3efa97b84e
|
[core] support coordinate on clock taps
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2024-06-26 17:40:11 -07:00 |