tangxifan
|
6dd8d347e1
|
try to deploy microbenchmark test_mode_low but fail due to .v port mismatch with .blif
|
2020-06-11 19:31:01 -06:00 |
CHARAS SAMY
|
f6cea1e17c
|
Added test_mode_low benchmark
|
2020-06-11 19:31:01 -06:00 |
|
CHARAS SAMY
|
3c781b18d3
|
Added routing benchmark
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
42cede37fa
|
add testcases on generate fabric/testbench only
|
2020-06-11 19:31:01 -06:00 |
|
tangxifan
|
9bf91bd92a
|
start testing mcnc_big20 using OpenFPGA tasks
|
2020-06-11 19:30:55 -06:00 |
ganeshgore
|
c31b20dc91
|
Added support for simulation setting file in the task flow
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
49edeb119c
|
BugFix : Relative path for refrence benchmark fixed
|
2020-06-11 19:28:13 -06:00 |
|
ganeshgore
|
890ead91b9
|
Fixed modelsim include references
|
2020-06-11 19:28:13 -06:00 |
|
tangxifan
|
90f608baea
|
changing task mcnc file for debugging (temporarily now) Will be corrected later
|
2020-04-23 18:58:39 -06:00 |
|
tangxifan
|
417d534121
|
fine tune mcnc example script to run Modelsim simulations easily
|
2020-04-23 16:15:45 -06:00 |
|
tangxifan
|
df85175765
|
fine tuning on mcnc example script so that we can run run_modelsim.py --runsim
|
2020-04-22 21:44:52 -06:00 |
|
tangxifan
|
f9fcc6b471
|
tweak mcnc scripts by stop VRP to remove buffers. Now passed mcnc big20 in Verilog/Bitstream generation
|
2020-04-22 18:24:09 -06:00 |
|
tangxifan
|
726185cd5e
|
add test cases using spypad architecture
|
2020-04-22 12:56:57 -06:00 |
|
tangxifan
|
73e9006372
|
add arch file with spy pads
|
2020-04-22 12:56:09 -06:00 |
|
tangxifan
|
9fb8971281
|
add FPGA arch with spypads to portofilo
|
2020-04-22 11:12:28 -06:00 |
|
tangxifan
|
9761d13eef
|
update microbenchmark and2 module name
|
2020-04-20 13:37:39 -06:00 |
|
tangxifan
|
489ca75230
|
adapt benchmark and_latch module name to be different than benchmark and
|
2020-04-20 13:15:05 -06:00 |
|
tangxifan
|
f6b7583a2a
|
add tasks for single mode
|
2020-04-20 12:55:40 -06:00 |
|
tangxifan
|
8b03ec900f
|
fine-tune micro benchmark to fit port mapping in testbenches
|
2020-04-19 17:05:12 -06:00 |
|
tangxifan
|
e10cafe0a5
|
Critical patch on repacking about wire LUT support.
Previously, the wire LUT identification is too naive and does not consider all the cases
|
2020-04-19 16:42:31 -06:00 |
|
tangxifan
|
32ed609238
|
update micro benchmark set and regression tests using them
|
2020-04-19 12:49:07 -06:00 |
|
tangxifan
|
98878f474b
|
light change on arch file to accelerate mcnc big20 run
|
2020-04-19 12:03:31 -06:00 |
|
tangxifan
|
cc163081f5
|
recover mcnc big20 test configuration
|
2020-04-18 21:06:43 -06:00 |
|
tangxifan
|
2e3a811f4f
|
critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results
|
2020-04-18 21:04:46 -06:00 |
|
tangxifan
|
f76a3090c4
|
add mcnc big20 test cases and start debugging
|
2020-04-18 19:25:16 -06:00 |
|
tangxifan
|
95863e996a
|
minor update on arch to use auto layout sizing
|
2020-04-18 18:43:56 -06:00 |
|
tangxifan
|
2f3a36ee81
|
update timing and rename the arch file
|
2020-04-18 18:39:47 -06:00 |
|
tangxifan
|
7ce34be175
|
update sample architecture timing
|
2020-04-17 22:06:06 -06:00 |
|
tangxifan
|
2ea4b8a2a2
|
add more flagship architectures
|
2020-04-17 19:12:27 -06:00 |
|
tangxifan
|
2ffd174e6a
|
fixed a bug in single mode FPGA; add arch to regression test; deploy full testbench verification on Travis CI
|
2020-04-15 15:48:33 -06:00 |
|
tangxifan
|
032ebc29e6
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-04-15 12:53:20 -06:00 |
|
tangxifan
|
1e742a3676
|
add test case on auto-check test benches
|
2020-04-15 12:52:52 -06:00 |
|
ganeshgore
|
689c4a3e19
|
BugFix: The filename in the previous commit
|
2020-04-15 12:44:22 -06:00 |
|
tangxifan
|
46fe1e84ce
|
Merge branch 'dev' into ganesh_dev
|
2020-04-15 12:27:51 -06:00 |
|
ganeshgore
|
7f37bf1441
|
Added formal verification support to fpga_flow script
|
2020-04-15 12:24:51 -06:00 |
|
tangxifan
|
7ba3e27371
|
add duplicated_grid_pin test case to Travis CI
|
2020-04-12 20:10:51 -06:00 |
|
tangxifan
|
e78643f108
|
add flatten routing test case to Travis CI
|
2020-04-12 20:06:40 -06:00 |
|
tangxifan
|
59ea0a6ad5
|
add implicit verilog test case to Travis CI
|
2020-04-12 20:00:20 -06:00 |
|
tangxifan
|
23aef96d3a
|
add behavioral verilog test case to Travis CI
|
2020-04-12 19:55:47 -06:00 |
|
tangxifan
|
11e9014542
|
add notes about debugging the aib FPGA
|
2020-04-12 19:07:53 -06:00 |
|
tangxifan
|
a614e5aad9
|
add long adder chain to Travis CI
|
2020-04-12 15:43:19 -06:00 |
|
tangxifan
|
f71a85a1d4
|
add test cases on different routing multiplexer circuit designs to Travis CI
|
2020-04-12 15:39:45 -06:00 |
|
tangxifan
|
214d98fbcd
|
add register chain and scan chain to Travis CI
|
2020-04-12 15:28:22 -06:00 |
|
tangxifan
|
148cc74d6a
|
add io test cases to Travis CI
|
2020-04-12 15:01:47 -06:00 |
|
tangxifan
|
da5af8f0e0
|
try to add aib test case. bug found
|
2020-04-12 14:54:45 -06:00 |
|
tangxifan
|
28cb412359
|
add test case of wide BRAM 16k to Travis CI
|
2020-04-12 14:37:08 -06:00 |
|
tangxifan
|
5d665aa04b
|
reshape bram test case
|
2020-04-12 14:32:09 -06:00 |
|
tangxifan
|
600a48edc7
|
add test case of BRAM to Travis CI
|
2020-04-12 14:27:05 -06:00 |
|
tangxifan
|
2444752de8
|
add untileable test case to Travis CI
|
2020-04-12 14:08:24 -06:00 |
|
tangxifan
|
d806ad3148
|
add testcases using openfpga_shell in openfpga_flow
|
2020-04-12 12:54:21 -06:00 |