tangxifan
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0565ca7aca
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[script] add missing files
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2022-09-29 16:14:38 -07:00 |
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tangxifan
|
ce0fbe1765
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[test] fixed a few bugs
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2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
9bc9b61d35
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[test] fixed a few bugs
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2022-09-29 15:11:30 -07:00 |
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tangxifan
|
f5e7ec4dd1
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[test] add a new test case to validate wire lut case
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2022-09-29 14:28:59 -07:00 |
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tangxifan
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b630d60b7e
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[test] update arch bitstream and force a pin placement for the test case where external bistream is fixed
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2022-09-20 14:14:18 -07:00 |
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tangxifan
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c48f750f86
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[test] now reduce the size for ql memory bank from 96x96 to 72x72; 96x96 requires >15G memory which exceeds github runner machine's RAM limit
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2022-09-01 20:10:29 -07:00 |
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tangxifan
|
9832722056
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[test] now add QuickLogic memory bank to fpga bitstream regression tests
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2022-05-25 11:42:32 +08:00 |
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tangxifan
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86347a9d49
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[test] move generate_bitstream to another directory. Ready to test generate bitstream across different configuration protocols
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2022-05-25 11:19:49 +08:00 |
Aram Kostanyan
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758453f725
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Moved 'verific_*' and 'yosys_*' config options from 'OpenFPGA_SHELL' to 'Synthesis Parameter' sections.
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2022-01-21 02:21:00 +05:00 |
|
Aram Kostanyan
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6a4cc340a3
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Changed HDL files reading to be as a single compilation unit in yosys_vpr flow for Verific mode. Changed '' variable to 'read_verilog ' in yosys template scripts. Updated task configs accordingly.
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2022-01-17 13:21:29 +05:00 |
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tangxifan
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ff264c00a2
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-31 11:51:34 -07:00 |
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tangxifan
|
c8e9dfbeda
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[Test] bug fix
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2021-10-30 16:50:57 -07:00 |
|
tangxifan
|
335347a74f
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[Test] Bug fix
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2021-10-30 15:48:25 -07:00 |
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tangxifan
|
be47e78289
|
[Arch] Change arch for Sapone test
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2021-10-30 15:23:19 -07:00 |
|
tangxifan
|
ad5cce0ae8
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[Test] Use frac_ff arch for SAPone; Otherwise Yosys cannot map reset signals
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2021-10-30 15:11:07 -07:00 |
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tangxifan
|
16de60e943
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[Test] Turn off ACE2 run in bitstream generation only flows
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2021-10-30 12:31:14 -07:00 |
|
tangxifan
|
189ade6c1e
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[Test] Bug fix
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2021-10-05 19:17:34 -07:00 |
|
tangxifan
|
f74ea5d39a
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[Test] Use the new openfpga shell script in don't care bit tests
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2021-10-05 19:14:44 -07:00 |
|
tangxifan
|
50604e4589
|
[Test] move test cases
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2021-10-05 19:02:43 -07:00 |
|
tangxifan
|
fed6c133b1
|
[Test] Add new tests to validate the correctness of bitstream files with don't care bits
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2021-10-05 18:59:33 -07:00 |
|
tangxifan
|
2baf3ddd2f
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[Test] Add test cases for 'report_bitstream_distribution' command
|
2021-05-07 12:06:24 -06:00 |
|
tangxifan
|
b8ced5377f
|
[Test] Add a test case for i/o mapping writer
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2021-04-27 14:41:15 -06:00 |
|
tangxifan
|
578d81b67a
|
[Test] Patch task configuration file
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2021-04-19 16:15:00 -06:00 |
|
tangxifan
|
5976cc0a1c
|
[Test] Add test case for using bitstream setting to overload default paths for pb_type interconnection
|
2021-04-19 15:54:18 -06:00 |
|
tangxifan
|
e19fc15fec
|
[Test] bug fix in test case
|
2021-02-18 19:37:45 -07:00 |
|
tangxifan
|
2e88b035ed
|
[Test] Add wire LUT repacker test case
|
2021-02-18 19:37:44 -07:00 |
|
tangxifan
|
655da9f3d0
|
[Flow] Rename OpenFPGA shell script folder name to consistent with naming convention
|
2020-11-22 16:37:19 -07:00 |
|
tangxifan
|
efad0402c2
|
[Regression Test] Bug fix for CI errors
|
2020-09-24 13:55:41 -06:00 |
|
tangxifan
|
e4291eb27e
|
[Regression Tests] Now use fixed device layout in test cases for best coverage
|
2020-09-21 18:44:13 -06:00 |
|
tangxifan
|
f33422d4d7
|
add regression test to track runtime on big fpga devices using practical benchmarks
|
2020-07-28 12:38:42 -06:00 |
|
tangxifan
|
5d83abb2cf
|
bug fix in read architecture bitstream and regression tests
|
2020-07-27 19:37:05 -06:00 |
|
tangxifan
|
5595ee9052
|
refine the test case for load external arch bitstream
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2020-07-27 16:53:29 -06:00 |
|
tangxifan
|
cec6bf0b6f
|
add or2 microbenchmark for testing external arch bitstream
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2020-07-27 15:59:03 -06:00 |
|
tangxifan
|
4174fbf77d
|
add load architecture bitstream test case and reorganize regression tests in category of openfpga tools
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2020-07-27 15:54:46 -06:00 |