tangxifan
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179ae355d0
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[Test] Do not run icarus verification for non const input test case. Icarus cannot handle the comb. loops
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2020-10-13 12:02:26 -06:00 |
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tangxifan
|
97c3bf7ea0
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[Test] Add a test case for non-constant input multiplexers
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2020-10-13 11:58:17 -06:00 |
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tangxifan
|
c5bcd93408
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[Architecture] Add the example architecture where std cell-based multiplexers do not have a constant input
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2020-10-13 11:57:21 -06:00 |
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tangxifan
|
99b1e68d92
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[Architecture] Add architecture using GND as constant inputs for multiplexers
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2020-10-13 11:39:27 -06:00 |
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tangxifan
|
570b494df7
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[Test] Add test case for using GND signal as constant input for routing multiplexers
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2020-10-13 11:38:54 -06:00 |
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tangxifan
|
dc68c52d0a
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[Test] Now use a light architecture to speed up the test case runtime
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2020-10-12 12:53:34 -06:00 |
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tangxifan
|
e59377a3ec
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[Flow] bug fix in the sample script for fabric netlist customization
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2020-10-12 12:52:01 -06:00 |
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tangxifan
|
8941e38613
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[Test] Enable verification in the new test case
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2020-10-12 12:50:08 -06:00 |
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tangxifan
|
9e1fd300dc
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[Test] Add test case for customized location of fabric netlists
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2020-10-12 12:47:58 -06:00 |
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tangxifan
|
e510e79c12
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[Flow] Add openfpga shell example script to use fabric netlist option
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2020-10-12 12:42:43 -06:00 |
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tangxifan
|
82e7b159ce
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[Regression test] Add test case for fracturable LUT using AND gate to switch modes
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2020-10-10 20:26:41 -06:00 |
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tangxifan
|
d0014878d5
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[Architecture] Add an openfpga architecture using and gate to control fracturable LUT modes
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2020-10-10 20:24:57 -06:00 |
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tangxifan
|
d4d02ab16a
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[Regression Test] Move fabric key tests to basic tests
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2020-09-29 14:22:23 -06:00 |
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tangxifan
|
ff6570df9d
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[Regression Test] Bug fix for fabric key test cases using multiple regions and deploy tests to CI
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2020-09-29 14:19:40 -06:00 |
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tangxifan
|
4f00d310d3
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[Architecture] Add example fabric key using multiple regions
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2020-09-29 14:14:50 -06:00 |
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tangxifan
|
02ea639959
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[Regression Test] Add test for fabric key based on multiple region
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2020-09-29 14:13:38 -06:00 |
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tangxifan
|
a0d1d68402
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[Regression Test] Add regression tests for smart fast configuration chain using multiple regions
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2020-09-29 13:53:41 -06:00 |
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tangxifan
|
d5c7411399
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[Architecture] Add more architecture to test fast configuration support on the multi-region configuration chain
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2020-09-29 13:50:31 -06:00 |
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tangxifan
|
5be5835b71
|
[Regression Test] Add multiple region configuration chain test case
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2020-09-29 13:48:39 -06:00 |
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tangxifan
|
23449dc5c3
|
[Architecture] Add multiple region configuration chain architecture
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2020-09-29 13:46:40 -06:00 |
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tangxifan
|
e09e5fa6c6
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[Architecture] Update fabric key for region syntax
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2020-09-27 20:40:37 -06:00 |
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tangxifan
|
ffd926d686
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[Architecture] Update external bitstream
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2020-09-25 21:30:59 -06:00 |
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tangxifan
|
dcbd6a0614
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[Architecture] Add lib name to TGATE to test compatibility
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2020-09-25 21:08:12 -06:00 |
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tangxifan
|
019208ec0f
|
[Architecture] Reorganize the cell netlists and update architecture files accordingly
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2020-09-25 11:55:28 -06:00 |
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tangxifan
|
20d6b2bf84
|
[Architecture] Remove out-of-date Verilog testbench
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2020-09-24 21:14:13 -06:00 |
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tangxifan
|
00bf775971
|
[Architecture] Bug fix for adder renaming
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2020-09-24 20:54:18 -06:00 |
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tangxifan
|
0a53a719bd
|
[Architecture] Bug fix due to adder renaming
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2020-09-24 20:42:24 -06:00 |
|
tangxifan
|
e4bfa2ef51
|
[Architecture] Update external bitstream file
|
2020-09-24 20:16:50 -06:00 |
|
tangxifan
|
bd0f0144a0
|
[Architecture] Rename AIB architecture for the new cell naming
|
2020-09-24 20:14:16 -06:00 |
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tangxifan
|
8edfc79f53
|
[Architecture] Rename AIB cell
|
2020-09-24 20:11:21 -06:00 |
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tangxifan
|
4ada793c84
|
[Architecture] Adapt openfpga architecture to follow the renamed adder cell
|
2020-09-24 20:09:29 -06:00 |
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tangxifan
|
53187044e6
|
[Architecture] Rename adder cell
|
2020-09-24 20:07:57 -06:00 |
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tangxifan
|
4a0a448171
|
[Architecture] Rename openfpga architecture for the I/O cell
|
2020-09-24 19:56:01 -06:00 |
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tangxifan
|
e0f9547f5b
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[Architecture] Rework the i/o cell Verilog HDL
|
2020-09-24 19:53:54 -06:00 |
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tangxifan
|
eb5fd1f44e
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[Architecture] Bug fix for architectures using scan-chain DFF cell
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2020-09-24 18:37:25 -06:00 |
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tangxifan
|
60a14ccbd2
|
[Architecture] Bug fix in architectures that use BRAM
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2020-09-24 18:20:55 -06:00 |
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tangxifan
|
d51efd397f
|
[Architecture] Bug fix for architectures using DFF cells
|
2020-09-24 18:02:42 -06:00 |
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tangxifan
|
3ade6d6ff5
|
[Architecture] Bug fix for dff that are used in data path
|
2020-09-24 17:53:30 -06:00 |
|
tangxifan
|
3e7c88eac8
|
[Architecture] Bug fix in Verilog netlist for scan-chain DFF
|
2020-09-24 17:41:03 -06:00 |
|
tangxifan
|
7494556316
|
[Architecture] Bug fix for scan-chain FF cell
|
2020-09-24 17:38:16 -06:00 |
|
tangxifan
|
54b3f244d3
|
[Architecture] Remove obsolete Verilog netlists
|
2020-09-24 17:35:02 -06:00 |
|
tangxifan
|
49d6863641
|
[Architecture] Bug fix for scan-chain FF cell renaming
|
2020-09-24 17:33:14 -06:00 |
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tangxifan
|
0a5369f919
|
[Architecture] Adapt all the architecture files to use standard DFF cell
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2020-09-24 17:26:48 -06:00 |
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tangxifan
|
19dd3778d9
|
[Architecture] Add test case for memory bank to use both reset and set
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2020-09-24 17:04:24 -06:00 |
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tangxifan
|
335f5b78c1
|
[Regression Test] Add test case to use both set and reset for configuration frame
|
2020-09-24 17:02:28 -06:00 |
|
tangxifan
|
2d81ff9012
|
[Regression test] Add configuration chain test case where both set and reset are used
|
2020-09-24 16:59:52 -06:00 |
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tangxifan
|
fc154b8560
|
[Architecture] Bug fix due to switching CCFF cell
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2020-09-24 16:45:56 -06:00 |
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tangxifan
|
79875d5a91
|
[Architecture] Bug fix in the configuration chain arch using both reset and set
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2020-09-24 15:27:26 -06:00 |
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tangxifan
|
9cb67e6097
|
[Architecture] Now all the configuration chain architecture use the DFFR cell by default
|
2020-09-24 15:19:37 -06:00 |
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tangxifan
|
81965e75f6
|
[Architecture] Bug fix in DFF Verilog HDL
|
2020-09-24 14:53:21 -06:00 |