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OpenFPGA
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3225 Commits

Author SHA1 Message Date
tangxifan a6354fab7c [Arch] Decide to move external bitstream definition to a separated XML file 2021-02-01 15:57:44 -07:00
tangxifan df88e2adc0 [Arch] Add an example definition of external bitstream to openfpga arch with soft adder 2021-02-01 14:26:11 -07:00
tangxifan 10302752a7 [Arch] Bug fix in architecture. Now soft adder modes are accepted 2021-02-01 13:43:39 -07:00
tangxifan d8927e12e8 [Arch] Add soft adder operating mode to test architecture 2021-02-01 12:25:37 -07:00
tangxifan 7f0f7a1c70 [Benchmark] Add micro benchmark 8-bit adder synthesized by Quicklogic script 2021-02-01 12:05:04 -07:00
tangxifan b215b868c1 [HDL] Bug fix in HDL netlist due to port name mismatching 2021-02-01 11:35:25 -07:00
tangxifan e4abe263c3 [Arch] Bug fix 2021-02-01 11:29:27 -07:00
tangxifan fb05e1a938 [Arch] bug fix due to using openfpga cell library 2021-02-01 11:27:21 -07:00
tangxifan 940dce469a [Test] Bug fix for test case configuration 2021-02-01 11:19:47 -07:00
tangxifan a80acfb547 [Test] Add new test case to CI script 2021-02-01 11:16:12 -07:00
tangxifan af630dab1e [Test] Add soft adder test case. This is placeholder. Test arch will be elaborated 2021-02-01 10:53:38 -07:00
tangxifan 9cce411eda [Test] Add adder test cases 2021-02-01 10:42:24 -07:00
tangxifan 0eb949b85a [Arch] Now use the MUX2 cell from openfpga cell library for the QLSOFA 2021-02-01 10:34:32 -07:00
tangxifan e0e2506e32 [HDL] Remove redundant comments 2021-02-01 10:33:08 -07:00
tangxifan 39543f7945 [HDL] Add carry mux2 to cell library 2021-02-01 10:23:46 -07:00
tangxifan 6ede799c16 [Arch] Add openfpga architecture for the QLSOFA 2021-02-01 10:15:35 -07:00
tangxifan f51aaae4a2
Merge pull request #208 from lnis-uofu/bump_yosys 
Bumping up yosys submodule as an option (-verilog) is added to write …
 2021-02-01 10:07:25 -07:00
tangxifan df05911d24 Merge branch 'master' into soft_adder_lut_support 2021-02-01 10:02:05 -07:00
Lalit Sharma 0f287fb539 Bumping up yosys submodule as an option (-verilog) is added to write verilog file 2021-02-01 13:43:31 +05:30
ganeshgore 186a0cadfb
Checking complete flow of build.yml from non master branch (#207) 
* [CICD] SHA extraction bug fix

* [CICD] Docker image builds but push from master

* [CICD] General cleanup
 2021-01-30 09:40:53 -07:00
tangxifan 20aebebcf2
Merge pull request #206 from lnis-uofu/gg_ci_cd_dev 
[CICD] Added SHA tag to docker build image
 2021-01-29 22:11:28 -07:00
ganeshgore d41ca7d2fd
Merge pull request #203 from lnis-uofu/dev 
Remove the hard requirement on signal activity file
 2021-01-29 21:29:01 -07:00
Ganesh Gore 52dc76c25e [CICD] Added SHA tag to docker build image 2021-01-29 20:22:45 -07:00
ganeshgore af8d750170
Merge pull request #205 from lnis-uofu/gg_ci_cd_dev 
[CICD] Checking master branch in change_detect
 2021-01-29 19:55:10 -07:00
tangxifan 9bbf214456 [Arch] Update the caravel architecture 2021-01-29 17:00:17 -07:00
Ganesh Gore 30277188db [CICD] Checking master branch in change_detect 2021-01-29 12:58:53 -07:00
tangxifan 0e16638dc2 [Doc] Update documentation about the changes on activity files 2021-01-29 11:49:07 -07:00
tangxifan a70725b4be Merge branch 'master' into dev 2021-01-29 11:41:40 -07:00
tangxifan 8b74947737 [Script] Now multi-clock openfpga shell script no longer needs activity file 2021-01-29 11:40:33 -07:00
tangxifan 4b77a3a574 [Tool] Now activity file is not a manadatory input of openfpga tools 2021-01-29 11:33:40 -07:00
ganeshgore bdf03c8b26
Bug fix on Docker build and upload on master (#202) 
* [CI/CD] Added force master image update option

* [CI/CD] Fixed .dockerignore while master image building

* [Test] checking correctness of source_modified flag

* [Bugfix] Fixed openfpga_flow in dockerignore

* [CICD] Added more context in dockerignore

* [CICD] Updated Dockerfile.master

* [CICD] Reverted test variables
 2021-01-29 11:16:57 -07:00
AurelienAlacchi 3f5cc59c0a
Microbenchmarks of Single-Port RAM and Associated Example Architecture Files as well as Test Cases (#200) 
* Add required files for LUTRAM integration and testing

* Add task for lutram

* Repair format (tab and space mismatched)

* Add disclaimer in architecture file

Co-authored-by: Aur??Lien ALACCHI <u1235811@lnissrv4.eng.utah.edu>
 2021-01-29 10:19:05 -07:00
ganeshgore 76845357f0
Merge pull request #199 from lnis-uofu/dev 
Version Echo of OpenFPGA Shell
 2021-01-28 11:03:21 -07:00
tangxifan 78ad9cd000 [Doc] Add version command/option to documentation 2021-01-27 16:06:45 -07:00
tangxifan d9fda31a9f [Tool] Add --version to openfpga shell option and a command to openfpga shell 2021-01-27 16:03:46 -07:00
ganeshgore 487bcd6734
[Bugfix] failing docker build + push on master branch (#196) 
* [Build] Added MAKE_FLAGS variable to Makefile
+ Mainly too provide -j parallel execution option

* [Yosys] Corrected output filename in QLyosys

* Revert "[Build] Added MAKE_FLAGS variable to Makefile"

This reverts commit c5e9da985a.

* [Shellrun] Added nested tasks to shortcuts

* Test on docker optimization pull request

* Optimized docekrfile.env

* Added parallel build option to cmake

* Reverted CMAKE parallel build

* Updated docker_regression_tests

* Corrected OPENFPGA_PATH in dockerfile

* Trying to merge  artifact_regression_tests and docker_distribution

* Revert "Trying to merge  artifact_regression_tests and docker_distribution"

This reverts commit fba6996d59.

* Added CI/CD documentation docs

* Code cleanup in flow and task script

* Saved regression artifcats in case of failure

* Logged exception in run command

* Checking failed regression test artifact upload

* Fixed yosys bug

* Removed travis and few unused local file

* Added -batch option in openfpga_flow script

* Upload artifacts for debug on failed regression test

* Added OpenFPGA shell info in logger print

* Updated docs

* [Backup] openfpga.sh backedup before pull request

* [CI/CD] Added extra runtime dependencies

* [CI/CD] Updated runtime enviroment to python3.8

* [CD/CD] Removed restalling depedencies, can be done by rebuilding images

* [Docs] Corrected typo

* [CI/CD] Moved pip installation to dockerfile

* [CI/CD] Running regression test with run-task

* [Python3.8] Added alternate python version

* [Bugfix] Fixed missing files/dir while building master docker image on origin/master branch

* Removed extra files

* Removed extra files 2
 2021-01-27 11:17:32 -07:00
tangxifan 38bd88873e
Merge pull request #197 from lnis-uofu/bump_yosys_adder 
Bumping the latest yosys changes related to soft_adder support
 2021-01-27 10:17:43 -07:00
Lalit Sharma c0126e6da7 Bumping the latest yosys changes related to soft_adder support 2021-01-27 03:40:17 -08:00
ganeshgore 114915862c
Merge pull request #194 from lnis-uofu/repo_cleanup 
Removing old dockerfile
 2021-01-26 22:55:13 -07:00
Ganesh Gore da8a1019b3 [Cleanup] Removed old docker build file 2021-01-26 22:35:11 -07:00
Ganesh Gore 5577d6a1b2 Merge remote-tracking branch 'origin/master' into repo_cleanup 2021-01-26 22:33:28 -07:00
ganeshgore 3cc780c522
Merge pull request #192 from lnis-uofu/repo_cleanup 
Removing unused files from the repo
 2021-01-26 22:32:18 -07:00
Ganesh Gore b0fd2569ca Merge remote-tracking branch 'origin/master' into repo_cleanup 2021-01-26 22:15:55 -07:00
tangxifan 56ceb1e4d6
Merge pull request #191 from lnis-uofu/python3_upgrade 
Upgrade Python3 to python 3.8
 2021-01-26 22:13:55 -07:00
Ganesh Gore 8f668df6d9 Merge remote-tracking branch 'origin/master' into python3_upgrade 2021-01-26 21:30:04 -07:00
tangxifan 39f8410bfd
Merge pull request #190 from lnis-uofu/ci_cd_docs 
[Docs] Added CI/CD docs
 2021-01-26 18:55:14 -07:00
Ganesh Gore 66de3dde59 [CI/CD] dropped old regressionn test 2021-01-26 17:58:03 -07:00
Ganesh Gore 646d299fa2 [CI/CD] dropped old regressionn test 2021-01-26 17:57:17 -07:00
Ganesh Gore 60e2e5cc9b [Cleanup] Removed unused files 2021-01-26 16:57:04 -07:00
Ganesh Gore 0b82b6439b [Regression] Upgraded runtime enviroment to python3.8 2021-01-26 16:40:45 -07:00