Commit Graph

3050 Commits

Author SHA1 Message Date
tangxifan 4aa6264b1c [Tool] Rework simulation time period to be sync with actual stimuli 2020-12-02 22:58:13 -07:00
tangxifan b661c39b04 [Tool] Force the number of simulation clock cycles to be >= 2 to avoid false-positive self-testing in testbenches 2020-12-02 19:36:36 -07:00
tangxifan d71f0537bc
Merge pull request #143 from lnis-uofu/dev
Critical Bug fix in the XML Syntax when Defining Default Values for A Global Tile Port
2020-12-02 18:41:25 -07:00
tangxifan 412fb5bb31 [Arch] Bug fix due to valid default value parser 2020-12-02 17:51:50 -07:00
tangxifan 8350b0f911 [Doc] Update documentation about default value definition in tile annotation 2020-12-02 17:08:34 -07:00
tangxifan d195b9e32c [Tool] Bug fix in XML syntax to define default values for a global tile port 2020-12-02 17:03:48 -07:00
Laboratory for Nano Integrated Systems (LNIS) 621f989c9b
Merge pull request #141 from LNIS-Projects/dev
Add a Test Case to CI which defines global reset port through tile port in VPR architecture
2020-12-01 08:41:57 -07:00
tangxifan 290ff028cd [Test] Add global_tile_reset test case to CI 2020-11-30 18:12:47 -07:00
tangxifan 179b0ce304 [Test] Use formal verification method to reduce the runtime of iverilog simulation for global tile 2020-11-30 18:11:47 -07:00
tangxifan c7604ab94f [Arch] Bug fix due to prog_reset port name conflicting with reserved words of OpenFPGA 2020-11-30 18:02:00 -07:00
tangxifan ff53d2c375 [HDL] Add new Scan-chain DFF cell 2020-11-30 17:54:10 -07:00
tangxifan ad703ad85b [HDL] Add new gpio cell with protection circuitry 2020-11-30 17:52:39 -07:00
tangxifan 27a480b5f8 [Test] arch name fix in the test case 2020-11-30 17:45:54 -07:00
tangxifan 7a0a3398d4 [Arch] Add new architecture to test global reset ports defined thru tile ports 2020-11-30 17:43:41 -07:00
tangxifan a1d3b439d3 [Test] Add a new test case to define a global reset port from a global tile port 2020-11-30 17:19:12 -07:00
Laboratory for Nano Integrated Systems (LNIS) 74828ee9ec
Merge pull request #139 from LNIS-Projects/dev
Update README with latest Github Action badge
2020-11-30 13:24:19 -07:00
tangxifan fc79e83e44 [Doc] Update README with latest Github Action badge 2020-11-30 11:57:08 -07:00
Laboratory for Nano Integrated Systems (LNIS) 8fde74542a
Merge pull request #135 from LNIS-Projects/dev
Support on Native Fracturable LUT Design
2020-11-26 13:55:37 -07:00
tangxifan cc0114459a [Doc] Enrich examples for LUT circuit models 2020-11-26 13:03:12 -07:00
tangxifan 62e804215b [Doc] Add svg figures for LUT examples 2020-11-26 12:35:39 -07:00
tangxifan dc5e2c99af [Test] Add native fracturable LUT4 test to CI 2020-11-25 23:02:18 -07:00
tangxifan 3a708cff21 [Tool] Bug fix to enable nature fracturable LUT design 2020-11-25 23:01:18 -07:00
tangxifan a60bd4d14a [Arch] Bug fix in nature fracturable architecture 2020-11-25 22:48:26 -07:00
ganeshgore 7db030018c [Bug] Fixed variable file location 2020-11-25 22:44:40 -07:00
tangxifan b8559249dc [Test] Bug fix in task configuration file 2020-11-25 22:23:27 -07:00
tangxifan 26e4db56ad [Test] Add new test case for the native fracturable LUT4 2020-11-25 22:21:23 -07:00
tangxifan 17070c6405 [Doc] Update README in openfpga arch directory for native fracturable LUT design 2020-11-25 22:19:20 -07:00
tangxifan f6a667de58 [Arch] Add openfpga architecture using native fracturable LUT 2020-11-25 22:18:03 -07:00
tangxifan eda671592e [Doc] Update README about new keyword about fracturable LUT 2020-11-25 22:12:56 -07:00
tangxifan 0f841aa6d1 [Arch] Add an example architecture using native fracturable LUT 2020-11-25 22:11:14 -07:00
ganeshgore 59bd7d0f18 [Flow] Changed substitute to safe_sustitute option 2020-11-25 22:09:36 -07:00
ganeshgore 91d3f289a8 [Build] Added python setup tools 2020-11-25 21:11:15 -07:00
ganeshgore febdd0896c [Build] Bux fix 2020-11-25 18:44:26 -07:00
ganeshgore bc90d53631 [Build] Corrected requirements file path 2020-11-25 18:35:15 -07:00
ganeshgore 2e4769feb9 [Build] Added python depenencies in CI/CD build 2020-11-25 18:10:26 -07:00
ganeshgore fefba0db59 Merge remote-tracking branch 'lnis_origin/master' into ganesh_dev 2020-11-25 17:29:53 -07:00
ganeshgore 1d993296d8 [Flow] Example of using test variable in task conf 2020-11-25 17:25:12 -07:00
ganeshgore 1554f583b7 [Flow] Now support explicit variable file for task 2020-11-25 17:22:41 -07:00
tangxifan a97efc4336
Merge pull request #131 from LNIS-Projects/dev
Improvements on Signal Initialization in Testbench Generation
2020-11-24 21:31:55 -07:00
tangxifan d2954f025f Merge branch 'master' into dev 2020-11-24 20:08:44 -07:00
Laboratory for Nano Integrated Systems (LNIS) e87f29784d
Merge pull request #133 from LNIS-Projects/github-actions-test
Use GitHub Actions as CI
2020-11-24 20:06:48 -07:00
tangxifan 96a99fcb6b [Test] Change to short build name and see if ccache is working or not 2020-11-24 18:58:06 -07:00
tangxifan df98c83d33 [Test] Keep trying the paths for ccache 2020-11-24 18:10:52 -07:00
tangxifan 91709abe80 [Test] Try to get the correct path to github workspace 2020-11-24 18:00:59 -07:00
tangxifan 9f956502b7 [Test] keep fixing the path to ccache file 2020-11-24 17:56:08 -07:00
tangxifan 6b757e2dca [Test] Bug fix in ccache path 2020-11-24 17:50:22 -07:00
tangxifan 0af1c0468e [Test] Spot cache file and try to use it 2020-11-24 17:41:27 -07:00
tangxifan df317271fd [Test] Try to check if .ccache is in the build directory 2020-11-24 16:54:55 -07:00
tangxifan c7d288c043 [Test] Try to new cache action version to see if problem is solved 2020-11-24 16:50:29 -07:00
tangxifan cba07b6020 [Test] Now travis and github actions share the common regression test scripts 2020-11-24 15:58:09 -07:00