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Merge pull request #131 from LNIS-Projects/dev 

Improvements on Signal Initialization in Testbench Generation
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tangxifan 2020-11-24 21:31:55 -07:00 committed by GitHub
parent e87f29784d d2954f025f
commit a97efc4336
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3 changed files with 41 additions and 8 deletions
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16
docs/source/manual/arch_lang/circuit_model_examples.rst
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@ -200,7 +200,15 @@ Template
<port type="output" prefix="<string>" size="<int>"/>
</circuit_model>
.. note:: Please do not add input and output buffers to pass-gate logic.
.. note:: The port sequence really matters! And all the input ports must have an input size of 1!
- The first input must be the datapath input, e.g., ``in``.
- The second input must be the select input, e.g., ``sel``.
- The third input (if applicable) must be the inverted select input, e.g., ``selb``.
.. warning:: Please do **NOT** add input and output buffers to pass-gate logic.
.. option:: <design_technology type="cmos" topology="<string>" nmos_size="<float>" pmos_size="<float>"/>
@ -376,6 +384,12 @@ Template
- ``topology="AND|OR|MUX2"`` Specify the logic functionality of a gate. As for standard cells, the size of each port is limited to 1. Currently, only 2-input and single-output logic gates are supported.
.. note:: The port sequence really matters for MUX2 logic gates!
- The first two inputs must be the datapath inputs, e.g., ``in0`` and ``in1``.
- The third input must be the select input, e.g., ``sel``.
.. _circuit_model_and2_example:
2-input AND Gate

6
docs/source/manual/fpga_verilog/testbench.rst
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@ -80,11 +80,13 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_fabric_verilog`` command.
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_fabric_verilog`` command.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.

27
openfpga/src/fpga_verilog/verilog_testbench_utils.cpp
View File

@ -747,6 +747,7 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
const std::string& hie_path,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model,
const std::vector<CircuitPortId>& circuit_input_ports,
const ModuleManager& module_manager,
const ModuleId& parent_module,
const ModuleId& primitive_module) {
@ -775,7 +776,7 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
if (child_module != primitive_module) {
rec_print_verilog_testbench_primitive_module_signal_initialization(fp,
child_hie_path,
circuit_lib, circuit_model,
circuit_lib, circuit_model, circuit_input_ports,
module_manager, child_module,
primitive_module);
} else {
@ -788,7 +789,7 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
fp << "\tinitial begin" << std::endl;
fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
for (const auto& input_port : circuit_input_ports) {
/* Only for formal verification: deposite a zero signal values */
/* Initialize each input port */
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
@ -801,12 +802,12 @@ void rec_print_verilog_testbench_primitive_module_signal_initialization(std::fst
fp << "\t`else" << std::endl;
/* Regular case: deposite initial signal values: a random value */
for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
for (const auto& input_port : circuit_input_ports) {
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
fp << "\t\t$deposit(";
fp << child_hie_path << ".";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
fp << ", $random);" << std::endl;
fp << ", $random % 2 ? 1'b1 : 1'b0);" << std::endl;
}
fp << "\t`endif\n" << std::endl;
@ -834,13 +835,29 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
/* Collect circuit models that need signal initialization */
std::vector<CircuitModelId> signal_init_circuit_models;
/* Collect the input ports that require signal initialization */
std::map<CircuitModelId, std::vector<CircuitPortId>> signal_init_circuit_ports;
for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_PASSGATE)) {
signal_init_circuit_models.push_back(model);
/* Only 1 input requires signal initialization,
* which is the first port, i.e., the datapath inputs
*/
std::vector<CircuitPortId> input_ports = circuit_lib.model_input_ports(model);
VTR_ASSERT(0 < input_ports.size());
signal_init_circuit_ports[model].push_back(input_ports[0]);
}
for (const CircuitModelId& model : circuit_lib.models_by_type(CIRCUIT_MODEL_GATE)) {
if (CIRCUIT_MODEL_GATE_MUX2 == circuit_lib.gate_type(model)) {
signal_init_circuit_models.push_back(model);
/* Only 2 input requires signal initialization,
* which is the first two port, i.e., the datapath inputs
*/
std::vector<CircuitPortId> input_ports = circuit_lib.model_input_ports(model);
VTR_ASSERT(1 < input_ports.size());
signal_init_circuit_ports[model].push_back(input_ports[0]);
signal_init_circuit_ports[model].push_back(input_ports[1]);
}
}
@ -860,7 +877,7 @@ void print_verilog_testbench_signal_initialization(std::fstream& fp,
/* Find all the instances created by the circuit model across the fabric*/
rec_print_verilog_testbench_primitive_module_signal_initialization(fp,
top_instance_name,
circuit_lib, signal_init_circuit_model,
circuit_lib, signal_init_circuit_model, signal_init_circuit_ports.at(signal_init_circuit_model),
module_manager, top_module,
primitive_module);
}