tangxifan
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b8d5920529
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Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into upstream
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2021-10-28 15:45:58 -07:00 |
Aram Kostanyan
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2eef21a1af
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Fixed port names for mult_36x36
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2021-10-26 19:14:43 +05:00 |
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tangxifan
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82e77b42c5
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[Arch] Add an example architecture which uses multiple shift register chain for a single-ql-bank FPGA
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2021-10-09 20:43:55 -07:00 |
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tangxifan
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d2859ca1c8
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[Arch] Add an example architecture for multi-region QuickLogic memory bank using shift registers
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2021-10-05 10:56:20 -07:00 |
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tangxifan
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fbef22b494
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[Arch] Bug fix in the example architecture for QL memory bank using WLR and shift registers
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2021-10-04 16:39:53 -07:00 |
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tangxifan
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86e7c963f8
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[Arch] Bug fix for wrong XML syntax in QuickLogic memory bank example architecture files
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2021-10-02 22:19:20 -07:00 |
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tangxifan
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7ba5d27ea7
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[Arch] Reworked example architectures for QuickLogic memory bank using shift registers: Add write-enable signal to WL CCFF model
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2021-10-01 17:02:35 -07:00 |
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tangxifan
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fa57117f50
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[Arch] Update openfpga architecture examples by adding syntax to identify clocks used by shift registers
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2021-10-01 10:19:51 -07:00 |
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tangxifan
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41cc375746
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[Arch] define default CCFF model in ql bank example architecture that uses shift registers
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2021-09-29 16:34:40 -07:00 |
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tangxifan
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4968f0d11f
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Merge branch 'master' into qlbank_sr
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2021-09-28 14:20:30 -07:00 |
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tangxifan
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80232fc459
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[Arch] Add a new example architecture for QL memory bank using WLR in shift registers
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2021-09-28 12:36:36 -07:00 |
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tangxifan
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4c04c0fbd7
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[Arch] Reworked the example architecture for QL memory bank using shift register by using the latest HDL models
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2021-09-28 12:35:42 -07:00 |
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tangxifan
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4aed045cdd
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[Arch] Added a new example OpenFPGA architecture which uses WLR signal in ql memory bank with flatten BL/WLs
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2021-09-28 11:34:20 -07:00 |
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tangxifan
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a98df811ed
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[Arch] Bug fix: wrong circuit model name was used for CCFF
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2021-09-22 15:50:47 -07:00 |
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tangxifan
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53da5d49fe
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[Arch] Correct XML syntax errors
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2021-09-22 15:48:14 -07:00 |
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tangxifan
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3cfd5c3531
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[Arch] Added an example architecture which uses shift-registers to configure BL/WLs for QL memory banks
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2021-09-22 15:04:59 -07:00 |
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tangxifan
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212c5bd642
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[Arch] Add an example architecture which uses flatten BL/WL for QL memory bank organization
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2021-09-22 15:04:19 -07:00 |
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tangxifan
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d0fe12fadd
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[Arch] Add an example OpenFPGA architecture for 2-region QL memory bank
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2021-09-22 10:03:39 -07:00 |
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tangxifan
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0450d57d82
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[Arch] Fixed critical bugs in the OpenFPGA architecture file for QL memory bank with WLR
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2021-09-20 16:05:01 -07:00 |
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tangxifan
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cd2978a434
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[Arch] Added a new architecture example which shows how to use the memory bank with readback functionality
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2021-09-20 11:13:02 -07:00 |
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tangxifan
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6be3c64f1c
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[Arch] Add an example architecture using the physical design friendly memory bank organization
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2021-09-09 09:22:27 -07:00 |
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tangxifan
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dcb89cb16b
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[Arch] Patch architecture due to missing mode bit definition
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2021-07-02 11:41:29 -06:00 |
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tangxifan
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fd85f956c9
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[Arch] Update k4n4 arch with true multi-mode flip-flop
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2021-07-02 11:08:39 -06:00 |
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tangxifan
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f77b81fe5b
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[Arch] recover the mem16k arch as it is used in other test cases
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2021-04-28 15:05:30 -06:00 |
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tangxifan
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117cea295d
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[Arch] Patch architecture to be compatible with pin names of DPRAM cell
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2021-04-28 11:28:23 -06:00 |
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tangxifan
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ec4b60f3cc
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[Arch] Add example arch using 1-kbit DPRAM
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2021-04-28 10:47:17 -06:00 |
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tangxifan
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be98775ae5
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[Arch] Reduce the size of DPRAM in example architecture to accelerate testing
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2021-04-28 10:45:10 -06:00 |
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tangxifan
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834657f2da
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[Arch] Patch arch using 16kbit DPRAM due to wrong addr sizes
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2021-04-27 23:41:14 -06:00 |
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tangxifan
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0f8aaae2bc
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[Arch] Patch architecture using 16kbit dual port RAM
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2021-04-27 19:54:34 -06:00 |
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tangxifan
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a3a98fa21d
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[Arch] Bug fix for port name mismatching between openfpga cell library and architecture definition
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2021-04-24 14:56:10 -06:00 |
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tangxifan
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4f454abfde
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[Arch] Add a new architecture using fracturable 16-bit DSP blocks
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2021-04-24 14:01:42 -06:00 |
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tangxifan
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ddcdb35b28
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[Arch] Bug fix in single-mode 8-bit DSP architectures
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2021-04-24 13:30:03 -06:00 |
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tangxifan
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ce6018e123
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[Arch] Enriched DFF model to support active-low/high FFs
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2021-04-21 22:48:31 -06:00 |
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tangxifan
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9d9840d9b7
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[Arch] Add architecture using multi-mode DFFs
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2021-04-21 19:49:48 -06:00 |
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tangxifan
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16e02ef485
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[Arch] patch architectures to be consistent with port mapping of custom DFF in yosys script
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2021-04-16 20:47:39 -06:00 |
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tangxifan
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4239bb4e68
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[Arch] Patch architecture files using multi-mode DFFs
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2021-04-16 19:59:55 -06:00 |
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tangxifan
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f2f7f010ea
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[Arch] Add new architectures using DFF with reset in VPR
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2021-04-16 19:26:18 -06:00 |
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tangxifan
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64294ae4eb
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[Doc] Update README for architecture files due to new architecture features
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2021-04-16 19:25:54 -06:00 |
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tangxifan
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44d97ead86
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Merge branch 'master' into hetergeneous_arch
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2021-03-23 17:05:03 -06:00 |
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tangxifan
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fdec72b5bc
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[Arch] Add an example architecture with 8-bit single-mode multiplier
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2021-03-23 15:35:06 -06:00 |
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tangxifan
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911979a731
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[Arch] Update heterogenous architecture for vtr benchmark by adding mult36
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2021-03-20 18:04:59 -06:00 |
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tangxifan
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910f8471dd
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[Arch] Add a representative heterogeneous FPGA architecture with single-mode BRAM (which can be synthesized by Yosys)
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2021-03-17 15:10:05 -06:00 |
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tangxifan
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baf162e401
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[Arch] Comment out dummy circuit model for adder_lut model in QL's cell sim library. which is no longer used in verification
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2021-03-10 22:45:19 -07:00 |
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tangxifan
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2daa770319
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[Arch] Update openfpga architecture to include quicklogic cell sim
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2021-03-08 21:40:29 -07:00 |
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tangxifan
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4c2a88e27f
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[Arch] Comment out yosys tech lib Verilog to see if it caused CI failed in iVerilog compilation; Now suspect that iVerilog v10.1 on CI is low; Local test with iVerilog v10.3 passed
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2021-02-24 11:51:10 -07:00 |
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tangxifan
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0ce9b66c75
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[Arch] Add a dummy adder lut circuit model to support HDL simulation
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2021-02-24 10:09:44 -07:00 |
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tangxifan
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ca135f3325
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[Arch] Add flagship architecture with 8-clock
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2021-02-22 15:01:18 -07:00 |
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tangxifan
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1c09c55e9f
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[Arch] Add hetergenenous 8-clock FPGA architecture
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2021-02-22 13:38:50 -07:00 |
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tangxifan
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0ac75723af
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[Arch] Add new architecture with 8 clocks
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2021-02-22 11:00:45 -07:00 |
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tangxifan
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d85d6e964e
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Merge pull request #227 from watcag/master
Standard-cell flow
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2021-02-17 10:11:34 -07:00 |