tangxifan
|
a1f19e776e
|
Add comments to lb router and extract a private function for routing a single net
|
2020-03-12 11:05:38 -06:00 |
|
tangxifan
|
cd50155e29
|
rename variables in lb router
|
2020-03-12 10:24:38 -06:00 |
|
tangxifan
|
17a1c61b9d
|
minor change in variable names in lb_router
|
2020-03-11 21:10:16 -06:00 |
|
tangxifan
|
8e796f152f
|
add comments to lb_router about how-to-use
|
2020-03-11 21:05:06 -06:00 |
|
tangxifan
|
2a260a05aa
|
add a microbenchmark `and_latch` to test LUTs in wired mode
|
2020-03-11 10:40:59 -06:00 |
|
tangxifan
|
1d766d2a70
|
minor format fix on documentation
|
2020-03-11 10:22:30 -06:00 |
|
Xifan Tang
|
b941ac8a4a
|
remove deprecated options
|
2020-03-10 20:58:00 -06:00 |
|
Xifan Tang
|
8037d1ad93
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2020-03-10 20:55:02 -06:00 |
|
Xifan Tang
|
9f743f7f4e
|
add openfpga shell documentation
|
2020-03-10 20:54:42 -06:00 |
|
tangxifan
|
0da6f00af5
|
start reworking the openfpga tool documentation
|
2020-03-10 17:29:35 -06:00 |
|
tangxifan
|
089cc5e86e
|
update documentation on circuit model annotation on VPR architecture
|
2020-03-10 16:51:50 -06:00 |
|
tangxifan
|
7195564455
|
reworked circuit model examples in documentation. Now we are consistent to latest syntax
|
2020-03-10 16:17:20 -06:00 |
|
tangxifan
|
8db257946c
|
remove backport in travis setup. The link is dead now. Plus we no longer need the backport for a newer version of cmake
|
2020-03-10 12:18:39 -06:00 |
|
tangxifan
|
54dfdc0cc1
|
update general documentation on circuit library
|
2020-03-10 12:18:12 -06:00 |
|
tangxifan
|
2a3c5b98a5
|
minor format fix in documentation
|
2020-03-09 21:25:13 -06:00 |
|
Xifan Tang
|
d14fa16905
|
finish documentation update on technology library
|
2020-03-09 21:17:25 -06:00 |
|
Xifan Tang
|
cb7e4a1dfa
|
finish documentation the simulation settings in VPR8 integration
|
2020-03-09 20:03:37 -06:00 |
|
tangxifan
|
751735bf41
|
update documentation in simulation setting syntax
|
2020-03-09 17:40:33 -06:00 |
|
tangxifan
|
3c7fd30e12
|
merged tutorial to online documentation and reworked compilation guidelines
|
2020-03-09 13:58:24 -06:00 |
|
tangxifan
|
af6319a6b0
|
reworked motivation in documentation
|
2020-03-09 11:27:25 -06:00 |
|
tangxifan
|
73da4a1d6e
|
rework motivation for FPGA-Verilog and FPGA-Bitstream in documentation
|
2020-03-09 10:32:03 -06:00 |
|
tangxifan
|
f821e60405
|
clean up deadlinks in doc
|
2020-03-09 10:15:16 -06:00 |
|
tangxifan
|
1f092171f2
|
Merge branch 'refactoring' into dev
|
2020-03-09 09:45:31 -06:00 |
|
tangxifan
|
d61ae5561b
|
start cleanup the documentation for openfpga shell
|
2020-03-09 09:44:19 -06:00 |
|
tangxifan
|
94d9b6e615
|
Merge branch 'refactoring' into dev
|
2020-03-09 09:35:59 -06:00 |
|
tangxifan
|
3aca7b498c
|
Show help desk when a command is called inside shell without satisfying the dependency
|
2020-03-09 09:34:21 -06:00 |
|
tangxifan
|
2f38b5cbc2
|
Merge branch 'refactoring' into dev
|
2020-03-08 16:23:20 -06:00 |
|
tangxifan
|
aff73bdd74
|
deployed edge sorting and make it as an option to link_arch command
|
2020-03-08 15:59:53 -06:00 |
|
tangxifan
|
b80e26e711
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |
|
tangxifan
|
5558932762
|
use sorted edges in building routing modules
|
2020-03-08 15:31:41 -06:00 |
|
tangxifan
|
7a7f8374b3
|
start deploying edge sorting in uniquifying SB modules
|
2020-03-08 15:24:34 -06:00 |
|
tangxifan
|
f9499afe04
|
remove unused variable
|
2020-03-08 15:00:01 -06:00 |
|
tangxifan
|
0c7aa2581d
|
update vpr8 version with hotfix on undriven pins in GSB
|
2020-03-08 14:58:56 -06:00 |
|
tangxifan
|
b219b096ee
|
hotfix on removing dangling inputs from GSB, which are CLB direct output
|
2020-03-08 13:54:49 -06:00 |
|
tangxifan
|
b2534f1a09
|
Merge branch 'refactoring' into dev
|
2020-03-07 23:31:45 -07:00 |
|
tangxifan
|
0fbf3fca41
|
start developing edge sorting inside RRGSB
|
2020-03-07 23:30:55 -07:00 |
|
tangxifan
|
8b40ca2990
|
Merge branch 'refactoring' into dev
|
2020-03-07 17:54:13 -07:00 |
|
tangxifan
|
ca92c2717f
|
bug fix for tile directs
|
2020-03-07 16:00:32 -07:00 |
|
tangxifan
|
e48c2b116d
|
bug fixing for duplicated grid pin names
|
2020-03-07 15:46:12 -07:00 |
|
tangxifan
|
37423729ec
|
bug fixing for naming the duplicated pins
|
2020-03-07 15:44:57 -07:00 |
|
tangxifan
|
3eeac94a6e
|
Merge branch 'refactoring' into dev
|
2020-03-06 20:58:07 -07:00 |
|
tangxifan
|
c36c302052
|
looks like tileable routing is working
|
2020-03-06 17:16:53 -07:00 |
|
tangxifan
|
f54f46483b
|
start debugging tileable rr_graph generator
|
2020-03-06 17:02:22 -07:00 |
|
tangxifan
|
5be118d695
|
tileable rr_graph builder ready to debug
|
2020-03-06 16:18:45 -07:00 |
|
tangxifan
|
245a379c4f
|
start plug in tileable rr_graph builder
|
2020-03-06 16:03:00 -07:00 |
|
tangxifan
|
3eb59d201f
|
adapt top function of tileable rr_graph builder
|
2020-03-06 15:24:26 -07:00 |
|
tangxifan
|
441a307100
|
add routing chan width corrector to rr_graph builder utils
|
2020-03-06 14:54:40 -07:00 |
|
tangxifan
|
441de12936
|
adapt Fc in gsb connection builder to use VPR8 Fc builder
|
2020-03-06 14:43:12 -07:00 |
|
tangxifan
|
ee4d5e46a0
|
Merge branch 'refactoring' into dev
|
2020-03-05 21:25:36 -07:00 |
|
tangxifan
|
8d350ee22f
|
adapt tileable rr_graph edge builder to rr_graph object
|
2020-03-05 20:50:21 -07:00 |