Commit Graph

134 Commits

Author SHA1 Message Date
tangxifan 475ce2c6d9 [Engine] Upgrade fabric generator in support QL memory bank connections 2021-09-05 17:49:01 -07:00
tangxifan ed80d6b3f4 [Engine] Place QL memory bank source codes in a separated source file so that integration to OpenFPGA open-source version is easier 2021-09-05 13:23:38 -07:00
tangxifan cf2e479d18 [Engine] Refactor the TopModuleNumConfigBits data structure 2021-09-05 12:01:38 -07:00
tangxifan f75456e304 [Engine] Update BL/WL estimation function for QL memory bank protocol 2021-09-05 11:53:33 -07:00
tangxifan 5759f5f35b [Engine] Start developing QL memory bank: upgrade infrastructures of fabric builder 2021-09-03 17:55:23 -07:00
tangxifan cbbf601edc [Tool] Fix a compiler warning due to uninitialized data structure 2021-06-18 16:20:13 -06:00
tangxifan c8d41b4e69 [Tool] Change routing module port naming to include architecture port names 2021-03-14 19:35:49 -06:00
tangxifan 956b9aca01 [Tool] Trim dead codes in port naming function 2021-03-13 20:23:08 -07:00
tangxifan 2c5634ee76 [Tool] Change pin naming of grid modules to be related to architecture port names 2021-03-13 20:05:18 -07:00
tangxifan e6091fb3ff [Tool] Now throw fatal error on mismatch in configurable regions between fabric key and architecture definition 2021-02-18 21:56:30 -07:00
tangxifan af4cc117fb [Tool] bug fix in spypad lut 2021-02-09 22:53:18 -07:00
tangxifan 6a0f4f354f [Tool] Support superLUT circuit model in core engine 2021-02-09 20:23:05 -07:00
tangxifan c0da6b900a [Tool] Bug fix in creating multi-bit clock port connections 2021-01-12 18:38:00 -07:00
tangxifan 65b2fe3ab7 [Tool] Bug fix in the global tile connection by considering all the subtiles 2021-01-10 11:52:38 -07:00
tangxifan 9a441fa5cc [Tool] Upgrade openfpga to support extended global tile port definition 2021-01-09 18:47:12 -07:00
tangxifan cde26597ed [Tool] Bug fix in scan chain builder calling 2021-01-04 18:45:47 -07:00
tangxifan 804b721a19 [Tool] Bug fix in the configuration chain connection builder 2021-01-04 17:41:29 -07:00
tangxifan bfd305b5a5 [Tool] Patch the bug in finding data output ports for CCFF 2021-01-04 17:22:30 -07:00
tangxifan cc91a0aebd [Tool] Patch the bug in port requirements for CCFF circuit model and now supports SCFF in module graph builder 2021-01-04 17:14:26 -07:00
tangxifan cb2bd2e31c [Tool] Remove register ports for mini local encoders (1-bit data out) 2020-12-06 14:21:54 -07:00
tangxifan 6bdfcb0147 [Tool] Bug fix for unifying mux primitive modules. Include memory size in the naming 2020-12-05 12:44:09 -07:00
tangxifan 6f18688f0e [Tool] Now routing multiplexer in the same circuit model (regardless or input sizes) can share the same primitive module 2020-12-05 10:53:01 -07:00
tangxifan 5be9e9b736 [Tool] Adapted tools to support I/O in center grid 2020-12-04 18:50:13 -07:00
tangxifan 3a708cff21 [Tool] Bug fix to enable nature fracturable LUT design 2020-11-25 23:01:18 -07:00
tangxifan 088198c861 [Tool] enhance error checking in fabric key parser 2020-11-13 10:56:00 -07:00
tangxifan 372fb261fd [Tool] Extend the support on global tile port for I/O tiles 2020-11-11 15:09:40 -07:00
tangxifan 9cbc374b33 [Tool] Add check codes for tile annotation 2020-11-11 12:03:13 -07:00
tangxifan c61ec5a8b8 [Tool] Bug fix for defining global ports from tiles 2020-11-10 20:31:14 -07:00
tangxifan dcb50e4f19 [Tool] Use use standard data structure to store global port information 2020-11-10 19:07:28 -07:00
tangxifan cbb1545ee3 [Tool] Add connection builder for tile global ports to top-level module 2020-11-10 16:59:00 -07:00
tangxifan 9b0617ffe6 [Tool] Bug fix for mappable I/O support 2020-11-04 20:45:51 -07:00
tangxifan 37c10f0cb5 [Tool] Add mappable I/O support and enhance I/O support 2020-11-04 20:21:49 -07:00
tangxifan 4a2874b2bc [Tool] Refactor the codes for walking through io blocks 2020-11-03 13:21:50 -07:00
tangxifan e4d974c5c8 [Tool] Split io location mapping builder from fabric builder 2020-11-02 18:27:34 -07:00
tangxifan 5bcd559851 [Tool] Many bug fix in the multi-region support for both memory banks and framed-based. Still have problems in multi-region framed-based verification 2020-10-30 17:29:04 -06:00
tangxifan 0d77916041 [Tool] Support multi-region frame-based configuration protocol 2020-10-30 10:43:11 -06:00
tangxifan 8ef6ae32fb [Tool] Bug fix for bitstream estimator due to the current special status of frame-based protocol 2020-10-29 17:35:55 -06:00
tangxifan 987eccf586 [Tool] Bug fix in multi-region memory bank; Basic test passed 2020-10-29 16:26:45 -06:00
tangxifan 448e88645a [Tool] Support multiple memory banks in top-level module 2020-10-29 12:42:03 -06:00
tangxifan bd49ea95d4 [Tool] Add function to comput configuration bits by region 2020-10-28 12:37:09 -06:00
tangxifan 446f982410 [Tool] Add warning when number of regions defined in fabric key is different than architecture 2020-10-28 11:43:05 -06:00
tangxifan e179a58b15 [OpenFPGA Tool] Bug fix for long runtime 2020-09-28 20:42:18 -06:00
tangxifan 47f3c79927 [OpenFPGA Tool] Bug fix in module manager due to configurable regions 2020-09-28 19:08:19 -06:00
tangxifan f93d46a870 [OpenFPGA Tool] Add multiple configuration chain support in top module builder 2020-09-28 19:03:19 -06:00
tangxifan 552dddffd0 [OpenFPGA Tool] Support configurable regions in module manager 2020-09-28 18:13:07 -06:00
tangxifan 052b8b71c7 [OpenFPGA Tool] Bug fix in the XML parser for fabric regions 2020-09-27 20:54:58 -06:00
tangxifan 6bea712db0 [OpenFPGA Tool] Bug fix in creating auto-generated cells using lib_name 2020-09-25 14:54:51 -06:00
tangxifan 9adeb550dc [OpenFPGA Tool] Bug fix in fabric builder 2020-09-23 18:28:00 -06:00
tangxifan f284f6f8d0 [OPENFPGA LIBRARY] change method names to be consistent with FPGA-SPICE needs 2020-09-20 12:03:10 -06:00
tangxifan 66e5e141a1 improve fabric key loader to reduce runtime 2020-07-07 10:19:34 -06:00