Lin
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41d0eb7736
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modification on device_rr_gsb
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2024-09-09 11:36:48 +08:00 |
Lin
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af7201d4bb
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fix is_compressed_ tag
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2024-09-09 11:19:12 +08:00 |
Lin
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a2b290c83b
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mod typo
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2024-08-30 15:47:29 +08:00 |
Lin
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94309c2a73
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change to reference
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2024-08-30 15:33:47 +08:00 |
Lin
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adeb9ba7ea
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fix typo
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2024-08-30 12:55:44 +08:00 |
Lin
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cb003f8833
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mod prelod flag
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2024-08-30 12:51:56 +08:00 |
Lin
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9e491680e6
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change file location
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2024-08-30 11:02:09 +08:00 |
Lin
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643e3a2dd1
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fix build bug
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2024-08-29 10:29:26 +08:00 |
Lin
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8372eead6a
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add preload flag to device_rr_gsb and revert change to build fabric
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2024-08-28 18:14:33 +08:00 |
Lin
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a23860a6a7
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reformat code
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2024-08-28 17:58:15 +08:00 |
Lin
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352c9b49c9
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add cmd dependency
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2024-08-28 17:52:34 +08:00 |
Lin
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df05c904db
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make the read block coord and read instance coords clearer
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2024-08-28 17:41:41 +08:00 |
Lin
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0a14b2fa65
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pass device_rr_gsb instead of openfpga_ctx
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2024-08-28 17:26:50 +08:00 |
Lin
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d4028b4e6f
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modification no build warning now
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2024-08-28 16:31:16 +08:00 |
Lin
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cde4c8d34a
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mod according to code review
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2024-08-28 15:45:19 +08:00 |
Lin
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1b0fcaee0f
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reformat code
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2024-08-27 17:05:13 +08:00 |
Lin
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3c28f84727
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build bug
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2024-08-26 19:21:26 -07:00 |
Lin
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9e283f383d
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remove redundant include
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2024-08-26 03:09:19 -07:00 |
Lin
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67c7c2da66
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mod comments
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2024-08-26 03:07:06 -07:00 |
Lin
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9c061e0ab5
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Merge branch 'preloading' of github.com:lnis-uofu/OpenFPGA
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2024-08-25 22:48:56 -07:00 |
Lin
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968824c2dd
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build unique blocks final version
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2024-08-25 19:56:23 -07:00 |
Lin
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913fdc043e
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debuged
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2024-08-23 03:52:16 -07:00 |
Lin
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699131ad58
|
full flow with bugs
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2024-08-19 01:18:06 -07:00 |
Lin
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a785a57520
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small bug mod
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2024-08-18 22:41:40 -07:00 |
tangxifan
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4b54e6fad1
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[core] fixed a corner case where spine usage should be updated after each switch point connection
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2024-08-15 20:12:31 -07:00 |
tangxifan
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642cb6eb9a
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[core] coord adjustment should occur based on des coord
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2024-08-15 14:28:29 -07:00 |
tangxifan
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c7da894eaf
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[core] fixed a bug where some spine was wrongly disabled
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2024-08-15 14:10:34 -07:00 |
tangxifan
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5877a3f7be
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[core] code format
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2024-08-15 12:44:03 -07:00 |
tangxifan
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00fd21704c
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[core] fixed a bug where the switch point coordinate of src spine required adjustment
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2024-08-15 12:41:09 -07:00 |
tangxifan
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1bcb0d0868
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[core] code format
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2024-08-14 18:09:44 -07:00 |
tangxifan
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4554c5781a
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[core] fixed a bug where some clock spine was wrongly marked unused
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2024-08-14 18:08:01 -07:00 |
tangxifan
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fc06aacc4e
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[core] code format
|
2024-08-14 10:49:36 -07:00 |
tangxifan
|
665777df51
|
[core] fixed some bug
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2024-08-14 10:49:12 -07:00 |
tangxifan
|
76e03e3e14
|
[core] code format
|
2024-08-13 23:25:04 -07:00 |
tangxifan
|
735adab9df
|
[core] syntax due to clang
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2024-08-13 23:24:28 -07:00 |
tangxifan
|
eb7639f44b
|
[core] code format
|
2024-08-13 22:37:34 -07:00 |
tangxifan
|
812686d169
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[core] support global net fixup in pb pin fixup
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2024-08-13 22:36:37 -07:00 |
tangxifan
|
ba5994a14c
|
[core] more debugging messages
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2024-08-13 21:03:49 -07:00 |
tangxifan
|
c2d9696489
|
[core] fixed a bug where some spines are not disabled
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2024-08-13 15:19:47 -07:00 |
tangxifan
|
ad13058a0b
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[core] fixed a bug where unused last-level of clock spines are not disabled
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2024-08-13 15:04:13 -07:00 |
tangxifan
|
4def678b11
|
[core] code format
|
2024-08-09 18:20:18 -07:00 |
tangxifan
|
1af1306444
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[core] fixed a bug where pin index for subtile is wrongly calculated for clock network taps
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2024-08-09 18:02:49 -07:00 |
tangxifan
|
f1ab44a212
|
[core] fixed a bug
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2024-08-09 17:10:58 -07:00 |
tangxifan
|
e4d7192e50
|
[core] fixed a bug where subtile was used for clock network tap name
|
2024-08-09 16:16:05 -07:00 |
Lin
|
755959a890
|
add cb cx write function
|
2024-08-08 02:54:02 -07:00 |
Lin
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e45619b22d
|
write sb
|
2024-08-08 01:00:35 -07:00 |
Lin
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9c67950a75
|
preload functions
|
2024-08-07 03:20:45 -07:00 |
tangxifan
|
1d5acea7e0
|
[core] typo
|
2024-08-06 20:17:15 -07:00 |
tangxifan
|
1225679aac
|
[core] code format
|
2024-08-06 17:35:44 -07:00 |
tangxifan
|
0dba4082d1
|
[core] syntax
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2024-08-06 17:20:34 -07:00 |