6fceb81110
[core] code format
2024-06-27 10:19:40 -07:00
64a7a4ce26
[core] syntax
2024-06-27 10:19:14 -07:00
9ce552495a
[core] now internal drivers can be routed in dedicated clock network
2024-06-27 10:17:08 -07:00
ac1ad52795
[core] code format
2024-06-26 22:47:29 -07:00
5d0b0b9a8c
[core] now global nets mapping are applied to clock routing
2024-06-26 22:46:12 -07:00
d5d9531eec
[core] comment out buggy codes where global net mapping is not annotated in OpenFPGA
2024-06-26 21:52:45 -07:00
59be95b227
[core] code format
2024-06-26 17:58:26 -07:00
59404e5487
[core] add verbose output
2024-06-26 17:55:23 -07:00
576a861b8d
[core] now skip routing any unused clock tree. Only connect to desired clock pin at programmable blocks
2024-06-26 17:54:31 -07:00
3efa97b84e
[core] support coordinate on clock taps
2024-06-26 17:40:11 -07:00
fbece49047
[core] fixed a bug where unexpected OPINs are added as internal drivers
2024-06-25 12:07:19 -07:00
7bcbd8a88b
[core] code format
2024-06-25 11:44:50 -07:00
3b2c13402a
[core] syntax
2024-06-25 11:44:25 -07:00
31d4b4c402
[core] now support add internal drivers to clock tree
2024-06-25 11:27:22 -07:00
d2053db21c
[core] removing the restrictions on only 1 clock tree is supported in programmable clock network
2024-06-21 19:00:01 -07:00
2193f108ee
[core] add debugging messages
2024-06-21 18:42:35 -07:00
3f08b83b3a
[core] remove restrictions on 1 clock tree definition
2024-06-21 17:12:10 -07:00
ecd31955b1
[core] code format
2024-06-21 17:11:32 -07:00
486cd01c15
[core] now clock graph builder supports two types of switches
2024-06-21 16:54:22 -07:00
ad8ad25250
[core] format
2024-05-31 19:44:40 -07:00
93ebbef851
[core] fixed a bug
2024-05-31 19:42:50 -07:00
514ec2f02e
[core] code format
2024-05-31 18:02:46 -07:00
2d10be9edb
[core] code comments
2024-05-31 18:00:24 -07:00
f9cd01636d
[core] fixed the bug where there is only 1 routing trace for a net which should be ignored (due to treated as global). This net should not be ignored unless there are >1 routing traces on the top-level pb. Then we can merge one.
2024-05-31 17:57:36 -07:00
212abecc27
[core] syntax
2024-05-31 17:41:49 -07:00
348d474bfd
[core] more debuggin messages
2024-05-31 17:40:19 -07:00
c565264e7d
[core] more debuggin messages
2024-05-31 17:14:42 -07:00
6dc31bf892
[core] fixed a bug on missing net sync up during repack
2024-05-31 16:53:59 -07:00
5b35f567d2
[core] detailed messages to trace why some nets are no sync
2024-05-31 16:00:10 -07:00
5adc1be204
[core] syntax
2024-05-31 15:50:27 -07:00
a9ccc277bd
[core] more debugging message
2024-05-31 15:49:34 -07:00
937e279c59
[core] adding more debugging messages
2024-05-31 15:43:51 -07:00
7a7fc679a8
[core] enable more debugging message in repacker
2024-05-31 14:52:59 -07:00
edb50f1b4d
[core] update debug messages
2024-05-31 14:37:46 -07:00
48c0b4b219
[core] fixed a bug where net name is not shown correctly on wire LUTs
2024-05-31 12:45:12 -07:00
74e94b855e
[core] fixed a bug where gsb OPIN name does not match the switch block module
2024-05-29 10:27:10 -07:00
52ae484a7c
[core] fixed a bug on messed up wire connections for OPINs
2024-05-20 13:50:31 -07:00
ca6e2f9831
[core] code format
2024-05-20 13:41:35 -07:00
4a791249bf
[core] fixed a bug on requirement wire model for direction connection which is part of a cb
2024-05-20 12:52:07 -07:00
b554a3d855
[core] code format
2024-05-19 17:24:38 -07:00
56aaa6a1f4
[core] sytax
2024-05-19 17:23:48 -07:00
065d77c679
[core] supporting opin connection to cb in tiles
2024-05-19 17:04:24 -07:00
9079056871
[core] now connect OPIN to CB in top-level module
2024-05-19 14:27:36 -07:00
918bf79ca3
[core] update vtr and developing caches for OPIN lists just for connection blocks
2024-05-19 14:10:00 -07:00
772da3006b
[core] code format
2024-05-18 22:19:17 -07:00
304f34525e
[core] syntax
2024-05-18 22:17:52 -07:00
b533ea4060
[core] now cb module include OPIN nodes
2024-05-18 22:00:02 -07:00
926b9e9739
[core] code format
2024-05-18 12:33:19 -07:00
3b93bea3d1
[core] syntax
2024-05-18 12:29:38 -07:00
0d8c21ca84
[core] add new type 'part_of_cb' for tile direct connections
2024-05-17 18:59:53 -07:00
7848bdaeac
[core] code format
2024-05-09 22:50:49 -07:00
5f37d63061
[core] fixed a bug where incoming edges are not built after loading rr_graph in vpr
2024-05-09 19:38:26 -07:00
7dc2c4951c
[core] add missing header required by clang-11+
2024-05-05 21:56:56 -07:00
3d8107487c
[core] code format
2024-05-03 10:21:39 -07:00
c7501cb9b7
[core] fixed the bugs when there are module renaming
2024-05-03 10:20:19 -07:00
f41a5e8b89
[core] fixed some bugs
2024-05-02 22:49:06 -07:00
c557b0104a
[core] avoid unwanted tab
2024-05-02 21:34:12 -07:00
b85ec28eb8
[core] code format
2024-05-02 21:17:17 -07:00
d3b1e562ad
[core] fixed some bugs on format
2024-05-02 21:11:20 -07:00
bf24382f19
[core] code format
2024-05-02 18:33:07 -07:00
a2fb84dfa9
[core] add fabric hierarchy writer
2024-05-02 18:30:20 -07:00
4d3447f773
[core] rework fabric hierarchy writer
2024-05-02 18:05:38 -07:00
dd577e37e0
LUTRAM Support ( #1595 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
* LUTRAM Support Phase 1
* Add Test
* Add more protocol checking to enable LUTRAM feature
* Move the config setting under config protocol
* Revert any changes
---------
Co-authored-by: chungshien-chai <chungshien.chai@gmail.com>
2024-04-19 14:46:38 -07:00
08bd6d00d3
[core] code format
2024-04-11 15:04:08 -07:00
79970719b4
[core] fixed a bug where regex breaks
2024-04-11 14:59:14 -07:00
f63ea06c4e
[core] now support regular expression in module name for fabric pin physical location output
2024-04-11 14:30:27 -07:00
5960cc14aa
[core] fixed a bug
2024-04-11 13:04:47 -07:00
6f94399767
[core] code format
2024-04-10 22:53:52 -07:00
971f0e8838
[core] add a new option '--show_invalid_side'
2024-04-10 22:52:36 -07:00
58708ff727
[core] syntax
2024-04-10 20:08:02 -07:00
435e83c530
[core] add port side to tile ports
2024-04-10 17:38:02 -07:00
f9f7d42d93
[core] add port side attribute and set them when buidling grid/cb/sb modules
2024-04-10 17:10:06 -07:00
d156de060e
[core] adding pin side attribute to module manager
2024-04-10 16:19:28 -07:00
b0be9fe75d
[core] developing xml writer for fabric pin phy loc
2024-04-10 15:51:26 -07:00
47baaff94c
[core] rename command name to 'write_fabric_pin_physical_location`` and start developing exec func
2024-04-10 13:30:02 -07:00
f1334645db
[core] added a new command write_pin_physical_location
2024-04-10 13:07:49 -07:00
0a7915aa77
[core] typo
2024-03-29 12:03:23 -07:00
6a5d3c7cdc
[code] syntax
2024-03-29 11:03:48 -07:00
00de794967
[core] code format
2024-03-29 10:58:48 -07:00
981828c39c
[core] add a new opton ``--dump_waveform`` to command ``write_preconfigured_fabric_wrapper``
2024-03-29 10:57:45 -07:00
4365d160ff
Support extracting data that is not affecting fabric bitstream ( #1566 )
...
* BRAM preload data - generic way to extract data from design
* Add docs and support special __layout__ case
* Add test
* Fix warning
* Change none-fabric to non-fabric
2024-03-09 17:38:31 -08:00
59deb97d5d
[core] code format
2024-01-12 14:17:10 -08:00
f1e3d53da6
[core] fixed a bug where pb pin fixup may fail when subtile capacities are not same
2024-01-12 14:16:07 -08:00
bacd845139
[core] code format
2023-12-08 13:41:41 -08:00
5e181cbe72
[core] add a new option for simulator type to verilog full testbench generator
2023-12-08 13:07:25 -08:00
0e945d6e71
[core] fix a bug in ql memory bank tb where VCS failed
2023-12-08 11:36:54 -08:00
8a24b1ba8c
Update repack_option.h
...
code clean up
2023-12-05 10:17:52 -08:00
94f7b2f4e2
Update repack.cpp
...
code clean up
2023-12-05 10:16:10 -08:00
d2379cfff6
Update repack_option.h
2023-12-05 09:34:34 -08:00
231cb0f89b
Update repack_option.cpp
2023-12-05 09:30:32 -08:00
83fdaea13d
Update repack.cpp
2023-12-05 09:28:27 -08:00
5ca928efda
Merge branch 'master' into repack_debug
2023-12-04 13:21:10 -08:00
c18f4d7f44
Issue:1466 - Fix WL ordering in bitstream generation
2023-11-29 21:55:53 -08:00
d28f024b61
minor change
2023-11-29 01:53:18 -08:00
1aac6681bc
Merge branch 'master' into repack_debug
2023-11-22 10:48:59 -08:00
e3682ac955
reformate the code
2023-11-22 01:15:55 -08:00
93d5b850f0
reset the error flag in each parsing iteration
2023-11-22 00:04:51 -08:00
8f9161b438
format the code
2023-11-21 22:28:37 -08:00
ee392f1b46
add ignore_net to repackdesign constraint
2023-11-21 21:47:03 -08:00
b780f0a552
[core] code format
2023-11-03 14:39:49 -07:00
e48de682ed
[core] fixed som ebugs
2023-11-03 14:39:28 -07:00
b2e1eb30c7
[core] code format
2023-11-03 13:50:04 -07:00
21813eb59f
[core] now full testbench uses bitstream in different sizes
2023-11-03 13:48:21 -07:00
2cd3453629
[core] fixed the bug in ccff v2 on config enable signal drivers
2023-11-03 10:25:12 -07:00
8bee65853c
[core] add missing files
2023-11-02 19:01:25 -07:00
649d44b2d8
[core] code format
2023-11-02 16:33:55 -07:00
36fa020c15
[core] syntax
2023-11-02 16:33:19 -07:00
75e9e98e5d
[core] add two new commands to output testbench parts
2023-11-02 16:06:48 -07:00
3d4f1505b6
[core] code format
2023-10-20 22:02:56 -07:00
66c3226fad
[core] now follow module unique index when naming grouped configuration memories
2023-10-20 22:01:19 -07:00
e4b204f2e4
[core] code format
2023-10-20 21:14:07 -07:00
76a4b8a82b
[core] remove the prefix of grouped memory blocks
2023-10-20 21:13:37 -07:00
5bae2bf54d
[core] code format
2023-10-19 23:05:49 -07:00
4b00651a46
[core] now name indexing is applied to netlist names
2023-10-19 23:03:48 -07:00
7ba6795fe2
[core] fixed a bug
2023-10-06 18:50:26 -07:00
83ef35b2da
[core] fixed a bug
2023-10-06 18:47:20 -07:00
3440768840
[core] code format
2023-10-06 18:37:54 -07:00
e102c9bddc
[core] fixed a bug
2023-10-06 18:37:28 -07:00
93cbbf2045
[core] code format
2023-10-06 18:20:55 -07:00
b07111497c
[core] enable options in xml writers
2023-10-06 18:20:17 -07:00
ae63c9d441
[core] code format
2023-10-06 17:28:25 -07:00
1e8bf1cece
[core] deploy options
2023-10-06 17:28:02 -07:00
f30663f708
[core] code format
2023-10-06 14:08:09 -07:00
108bbad8d4
[core] syntax
2023-10-06 14:07:44 -07:00
80856f1b70
[core] adding new options and rewrite options for bitfile writer
2023-10-06 13:54:29 -07:00
a15db83267
[core] code format
2023-09-26 11:41:11 -07:00
ea91182216
[core] check option conflicts
2023-09-26 11:40:42 -07:00
c4bce834e4
[core] code format
2023-09-25 22:34:39 -07:00
5aa206e616
[core] fixed some bugs
2023-09-25 22:27:24 -07:00
1624dc9764
[core] code format
2023-09-25 21:13:50 -07:00
76f446caec
[core] fixed a bug
2023-09-25 21:13:11 -07:00
dbd466cdec
[core] now support tile port merge
2023-09-25 18:16:24 -07:00
3adf81046a
[core] code format
2023-09-25 17:22:26 -07:00
5e269e8bc4
[core] support port merging at grid modules
2023-09-25 17:21:58 -07:00
edb0e687f1
[core] code format
2023-09-23 12:15:53 -07:00
11de8965a8
[core] fixed some bugs
2023-09-23 12:15:31 -07:00
860cfd53c6
[core] fixed critical bugs in renaming modules
2023-09-23 11:51:31 -07:00
ca3617a029
[core] code format
2023-09-20 20:37:27 -07:00
1ef38b6a64
[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
2023-09-20 20:34:21 -07:00
c105b56bf0
[core] code format
2023-09-18 23:31:27 -07:00
43fd08a3fe
[core] fixed a bug
2023-09-18 23:31:09 -07:00
4d11f73471
[core] fixed a bug
2023-09-18 20:43:15 -07:00
a1e609c901
[core] fixed some bugs
2023-09-18 16:39:07 -07:00
1daabb990e
[core] code format
2023-09-18 15:35:13 -07:00
110301a2e4
[core] now tile port naming can follow index
2023-09-18 15:34:40 -07:00
e46e58527a
[core] code format
2023-09-17 23:16:38 -07:00
eeb1bd6662
[core] fixed some bugs
2023-09-17 23:16:15 -07:00
c6175aa514
[core] code format
2023-09-17 22:37:48 -07:00
ef97127c63
[core] fixed some bugs in testbenches when renaming top modules
2023-09-17 22:34:00 -07:00
c14277a674
[core] fixing bugs
2023-09-17 17:57:57 -07:00
d5152dc16d
[core] fixed a bug on the hierarchy writer
2023-09-17 17:42:25 -07:00
4ccb4737be
[core] code format
2023-09-17 17:33:10 -07:00
f79da76656
[core] supporting renaming on all the verilog modules
2023-09-17 17:29:11 -07:00
72a3c05747
[core] code format
2023-09-17 13:29:30 -07:00
ccd4c1861b
[core] developing new command to write module naming rules
2023-09-16 19:37:06 -07:00
32df673d72
[core] code format
2023-09-16 18:35:33 -07:00
200ecad74a
[core] fixed bugs in bitgen
2023-09-16 18:34:55 -07:00
058bb1ef51
[core] code format
2023-09-16 18:24:38 -07:00
6fc2924438
[core] syntax
2023-09-16 18:16:30 -07:00
d61d88f12e
[core] fixed some bugs in verilog writer due to renaming
2023-09-16 18:13:22 -07:00
37573abc22
[core] code format
2023-09-15 23:32:40 -07:00
c85c64eb5a
[core] syntax
2023-09-15 23:30:34 -07:00
bc407e5d69
[core] code complete for rename modules
2023-09-15 23:22:31 -07:00
2a45b49890
[core] developing renaming commands. options and functions
2023-09-15 19:15:18 -07:00
af67b02cca
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
2023-09-15 13:51:14 -07:00
eaadff3448
[core] fixed some bugs
2023-09-06 22:49:56 -07:00
bcb82d43af
[core] code format
2023-09-06 22:40:59 -07:00
2fee56548b
[core] fixed some bugs
2023-09-06 22:39:59 -07:00
f544953085
[core] code format
2023-09-06 22:29:30 -07:00
f8b2eec988
[core] now default net type wire will not appear. timescale does not show in fabric netlists
2023-09-06 22:27:51 -07:00
539bcba851
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
2023-09-06 17:23:41 -07:00
dfe5447e2a
[core] format
2023-08-25 15:21:24 -07:00
b8c66b06a0
[core] syntax
2023-08-25 15:17:52 -07:00
717906ea17
[core] code format
2023-08-25 15:13:39 -07:00
89b392a51f
[core] adapt changes in is_sb_exist()
2023-08-25 15:13:00 -07:00
55e5f738ce
[core] code format
2023-08-25 11:58:15 -07:00
92f92658c9
[core] remove useless errors
2023-08-25 11:53:49 -07:00
a6d43beaca
[core] now tile verilog writer supports relative paths
2023-08-21 22:25:52 -07:00
66cc375996
[core] remove debugging messages
2023-08-18 22:08:47 -07:00
19d4d9a16d
[core] code format
2023-08-18 21:05:26 -07:00
fc523bed32
[core] fixed some bugs in spotting the correct pin index of given subtiles
2023-08-18 21:04:37 -07:00
3d8f76269a
[core] fixed a bug when io is in the center of 3x3 fabric
2023-08-18 12:42:15 -07:00
e9fd22790d
[core] fixed a bug where pass thru cb blocks are not connected in tiles
2023-08-17 15:26:32 -07:00
399f087c50
[core] code format
2023-08-17 13:54:31 -07:00
414f7379c6
[core] fixed some bugs in debugging messages
2023-08-17 13:52:21 -07:00
aabbd330b3
Address follow up from PR 1259 (1)
2023-08-11 08:06:57 -07:00
6c0df8da20
Address follow up from PR 1259
2023-08-11 07:59:53 -07:00
788e3c17a9
[core] format
2023-08-08 23:02:20 -07:00
1c8c4fedbb
[core] fix memory leak
2023-08-08 23:01:52 -07:00
ff6fa1e90c
[core] fix memory leak
2023-08-08 22:41:43 -07:00
94d80a9b7c
[core] code format
2023-08-08 16:28:56 -07:00
867da98d3f
[core] update to use latest api from vpr upstream
2023-08-08 16:28:19 -07:00
bb945b2816
Merge branch 'master' into openfpga-issue-1256
2023-08-07 13:49:19 -07:00
4d37421735
[core] fixed a bug on loading subkey to support fabric keys
2023-08-07 10:40:22 -07:00
18acb39fad
[core] fixed a bug where heterogeneous fabric may fail
2023-08-06 22:12:32 -07:00
26c8b5146c
[core] fixed a bug where release build will fail
2023-08-06 21:44:15 -07:00
c5b1918e47
[core] fixed a critical bug which causes reg test failures when group_config_block is off
2023-08-06 13:11:17 -07:00
beee2369c9
[core] fixed a bug
2023-08-05 22:06:17 -07:00
a1f8b3c441
[core] fixed a bug on bitstream generator on supporting group_config_block
2023-08-05 21:58:03 -07:00
68f07d6fc9
[core] code format
2023-08-05 20:53:58 -07:00
tangxifan
chungshien
Yitian4Debug
chungshien
ubuntu